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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/48660完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹(Hsin-Hsu Chen) | |
| dc.contributor.author | Hang-Quei Chiu | en |
| dc.contributor.author | 邱漢奎 | zh_TW |
| dc.date.accessioned | 2021-06-15T07:07:03Z | - |
| dc.date.available | 2013-12-10 | |
| dc.date.copyright | 2010-12-10 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-11-18 | |
| dc.identifier.citation | [1] E. Gaalaas, B. Y. Liu, N. Nishimura, R. Adams, and K. Sweetland, “Integrated stereo sigma-delta class d amplifier,” IEEE J. Solid-State Circuits, vol. 40, no. 12, Dec. 2005.
[2] K. Nielsen, “A review and comparison of pulse width modulation(pwm) methods for analog and digital input switching power amplifiers,” AES 102nd convention, Mar. 1997. [3] M. R. Hoque and S. S. Ang, “A cmos under-voltage lockout circuit,” in WCECS, Oct.22–24 2008. [4] J. Honda and J. Adams, “Class d audio amplifier design,” International Rectifier, 2003. [5] J. Cerezo, “Application note an-1070, class d audio amplifier performance relationship to mosfet parameters,” International Rectifier, 2004. [6] A. P. Inc., 2700 Series User’s Manual. Audio Precision, 2008. [7] ——, AUX-0025 User’s Manual. Audio Precision, 2003. [8] B. Forejt, “T1: Fundamental of class-d amplifier operation & design,” in ISSCC Tutorial, Feb.3 2008. [9] B. Putzeys, “Simple self-oscillating class d amplifier with full output filter control,” AES 118th convention, May 2005. [10] S. C. Li, V. C. Chang, K. Nandhasri, and J. Ngarmnil, “New high-efficiency 2.5 v/0.45 w rwdm class-d audio amplifier for portable consumer electronics,” IEEE Trans. Circuits Syst. I, vol. 52, no. 9, Sep. 2005. [11] C. Yoo, “A cmos buffer without short-circuit power consumption,” IEEE Trans. Circuits Syst. II, vol. 47, no. 9, Sep. 2000. [12] M. Berkhout, “Integrated overcurrent protection system for class-d audio power amplifiers,” IEEE J. Solid-State Circuits, vol. 40, no. 11, Nov. 2005. [13] P. Muggler, W. Chen, C. Jones, P. Dagli, and N. Yazdi, “A filter free class d audio amplifier with 86 % power efficiency,” in ISCAS, vol. 1, May23–26 2004. [14] M.-T. Tan, H.-C. Chua, B.-H. Gwee, and J. S. Chang, “An investigation on the parameters affecting total harmonic distortion in class d amplifiers,” in ISCAS, May28–31 2000. [15] W. Shu and J. S. Chang, “Thd of closed-loop analog pwm class-d amplifiers,” IEEE Trans. Circuits Syst. I, vol. 55, no. 6, Jul. 2008. [16] F. Koeslag, H. du T. Mouton, H. Beukes, and P. Midya, “A detailed analysis of the effect of dead time on harmonic distortion in a class d audio amplifier,” in AFRICON, Sep.26–28 2007. [17] W. Shu and J. S. Chang, “Power supply noise in analog audio class d amplifiers,” IEEE Trans. Circuits Syst. I, vol. 56, no. 1, Jan. 2009. [18] H. C. Foong and M. T. Tan, “An analysis of thd in class d amplifiers,” in APCCAS, 2006. [19] A. R. Oliva, S. S. Ang, and T. V. Vo, “A multi-loop voltage-feedback filterless class-d switching audio amplifier using unipolar pulse-width-modulation,” IEEE Trans. Consum. Electron., vol. 50, no. 1, Feb. 2004. [20] H. S. Black, Modulation Theory. New York: Van Norstrand, 1953. [21] T. Ge, J. S. Chang, W. Shu, and M. T. Tan, “Modeling and analysis of psrr in analog pwm class d amplifiers,” in ISCAS, 2006, pp. 1386–1389. [22] W. Shu, J. S. Chang, T. Ge, and M. T. Tan, “Fourier series analysis of the nonlinearities in analog closed-loop pwm class d amplifiers,” in ISCAS. IEEE, 2006. [23] T. Ge and J. S. Chang, “Bang-bang control class d amplifiers: Total harmonic distortion and supply noise,” IEEE Trans. Circuits Syst. I, vol. 56, no. 10, Oct. 2009. [24] G. Pillonnet, N. Abouchi, R. Cellier, and A. Nagari, “A 0.01% thd, 70db psrr single ended class d using variable hysteresis control for headphone amplifiers,” in ISCAS, 2009. [25] H.-S. Kim, S.-W. Jung, H.-M. Jung, J.-K. Shin, and P. Choi, “Low cost implementation of filterless class d audio amplifier with constant switching frequency,” IEEE Trans. Consum. Electron., vol. 52, no. 4, Nov. 2006. [26] S. Smith, Microelectronic Circuits, 5th ed. New York Oxford University Press, 2004. [27] T. Ge and J. S. Chang, “Bang-bang control class-d amplifiers: Power-supply noise,” IEEE Trans. Circuits Syst. II, vol. 55, no. 8, Aug. 2008. [28] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, 2nd ed. New York Oxford University Press, 2002. [29] B. Razavi, Design of Analog CMOS Integrated Circuits. McGRAW-Hill, 2001. [30] B. Metzler, Audio Measurement Handbook. Audio Precision, 2005. [31] M. A. Rojas-Gonzalez and E. Sanchez-Sinencio, “Design of a calss d audio amplifier ic using sliding mode control and negative feedback,” IEEE Trans. Consum. Electron., vol. 53, no. 2, May 2007. [32] S.-H. Jung, N.-I. Kim, and G.-H. Cho, “Class d audio power amplifier with fine hysteresis control,” IEEE Power Electron. Lett., vol. 38, no. 22, Oct. 2002. [33] S. Poulsen and M. A. E. Andersen, “Hysteresis controller with constant switching frequency,” IEEE Trans. Consum. Electron., vol. 51, no. 2, May 2005. [34] T. Ge, J. S. Chang, and W. Shu, “Power supply noise in bang-bang control class d amplifier,” in ISCAS, 2007, pp. 701–704. [35] T. Ge and J. S. Chang, “Modeling and technique to improve psrr and ps-imd in analog pwm class d amplifiers,” IEEE Trans. Circuits Syst. II, vol. 55, no. 6, Jun. 2008. [36] International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece. IEEE, 2006. [37] C. Pascual, Z. Song, P. T. Krein, D. V. Sarwate, P. Midya, and W. B. J. Roeckner, “High-fidelity pwm inverter for digital audio amplification: Spectral analysis, real-time dsp implementation, and results,” IEEE Trans. Power Electron., vol. 18, no. 1, Jan. 2003. [38] J. Honda and J. Adams, “Application note an-1071, class d audio amplifier basics,” International Rectifier, 2005. [39] M. Berkhout, “An integrated 200-w class d audio amplifier,” IEEE journal of solid-state circuits, vol. 38, no. 7, July 2003. [40] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, 2nd ed. New York Oxford University Press, 2002. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/48660 | - |
| dc.description.abstract | 本篇論文提出了一個較簡單的磁滯控制D類音頻放大器(class D audio amplifier, CDA)電路實現。此電路實現在D類音頻放大器的輸出級之前加上了額外的時間延遲來達到磁滯控制的功能，因此我們將此種控制稱做驅動延遲磁滯控制(driver delay hysteresis control, DDHC)。
論文當中分析了此種驅動延遲磁滯控制D類音頻放大器(DDHC CDA)的總諧波失真(total harmonic distortion, THD)及電源雜訊抑制比(power-supply rejection ratio, PSRR)。分析的結果顯示，傳統的磁滯控制D類音頻放大器中所擁有的失真及雜訊來源在此DDHC CDA當中完全被消除了。並且此DDHC CDA去除了傳統上PWM(pulse width modualation)調變的閉迴路D類音頻放大器(PWM CDA)所具有的高頻失真來源。量測及分析的結果均顯示，此DDHC CDA相較於PWM CDA在整個音頻範圍內具有較佳的THD。 所提出的DDHC CDA使用了3.3V 0.35μm 2P4M CMOS製程實作，主要電路區域面積為0.53x0.4 mm^2。量測的THD+N在20Hz到20kHz之間均低於0.03%。當電源雜訊為-30dBV，217Hz的標準GSM雜訊時，PSRR為64dB。量測得到的SNR(signal-to-noise ratio)為80dB。當最大輸出功率時，電路的輸出功率效率是80%。 | zh_TW |
| dc.description.abstract | A simple circuit implementation of hysteresis controlled class D amplifier(CDA) is proposed in the thesis. Since the proposed circuit puts additional delay before the gate driver and switching stage in CDA to realize the hysteresis control, new control method is called driver delay hysteresiscontrol(DDHC).
In this thesis, we analyse the total harmonic distortion(THD) and power supply rejection ratio(PSRR) of the proposed DDHC CDA. The analytical expression shows that the distortion source in the common hysteresis control(bang-bang control) CDA is completely dismissed in the DDHC CDA. The measurement results show that the proposed DDHC CDA has lower THD compared to PWM CDA in whole audio band. The proposed DDHC CDA is integrated and fabricated in 3.3V 0.35μm 2P4M CMOS process with 0.53x0.4 mm^2 active layout area. The measurement results show the THD+N ratio is flat and below 0.03% between 20Hz and 20kHz and PSRR is 64dB for a -30dBV,217Hz standard GSM perturbation noise. The measured SNR is 80dB at -60dB from full scale. The power efficiency is 80% at full power. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T07:07:03Z (GMT). No. of bitstreams: 1 ntu-99-R95943012-1.pdf: 5707393 bytes, checksum: 0bcbec69bf8c1fe2ad70b1a142b8cd3f (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | Concent 1
1 Introduction 10 1.1 Audio Amplifier Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 Linear and Switching Audio Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3 Audio Amplifier Design Trends and Challenges . . . . . . . . . . . . . . . . . . . . 12 1.4 Thesis Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Fundamentals of Class D Amplifier 14 2.1 Modulation Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.1 Pulse Width Modulation(PWM) . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.2 Pulse Density Modulation(PDM) . . . . . . . . . . . . . . . . . . . . . . . 17 2.1.3 Self-oscillation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.1.4 3-level PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2 Output Stage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.1 Dead Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.2 Overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.3 Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.4 Overheating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3 Power Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3.1 Conduction Loss, Pcond . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3.2 Switching Loss, Psw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3.3 Gate Driver Loss, Pgd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.4 Output Topology and Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.4.1 Half Bridge and Full Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.4.2 Second-order Butterworth Filter . . . . . . . . . . . . . . . . . . . . . . . . 29 2.4.3 No Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.5 Distortion/Noise Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3 Closed Loop Class-D Amplifier 34 3.1 PWM CDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.1.1 THD Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.1.2 PSRR Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.2 Bang-Bang Control CDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.2.1 Implementation Type-I: Passive Integrator . . . . . . . . . . . . . . . . . . . 39 3.2.2 Implementation Type-II: Active Integrator . . . . . . . . . . . . . . . . . . . 44 4 Proposed DDHC Class-D Amplifier 48 4.1 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.1.1 System Linear Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.1.2 DDHC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.1.3 Determine the Switching Frequency . . . . . . . . . . . . . . . . . . . . . . 51 4.1.4 THD Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.1.5 PSRR Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.1.6 THD Comparison of DDHC CDA and PWM CDA . . . . . . . . . . . . . . 55 4.2 Circuit Design ,Implementation and Simulation Results . . . . . . . . . . . . . . . . 56 4.2.1 Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.2.2 DDHC Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.2.3 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.2.4 Switching Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.3 Whole System Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.3.1 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.3.2 Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.3.3 Input and Output Spectrum/Waveform . . . . . . . . . . . . . . . . . . . . . 70 4.3.4 Harmonics Distortion and Noise Performance . . . . . . . . . . . . . . . . . 71 4.3.5 PSRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.3.6 Power Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5 Measurements 75 5.1 PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.1.1 DUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.1.2 Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.1.3 Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.2.1 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.2.2 Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.2.3 Input and Output Spectrum/Waveform . . . . . . . . . . . . . . . . . . . . . 84 5.2.4 Harmonics Distortion and Noise Performance . . . . . . . . . . . . . . . . . 85 5.2.5 PSRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.2.6 Power Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6 Conclusion 92 A Term Definitions 93 A.1 Modulation Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 A.2 dBV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 B Derivation of the Effective Hysteresis Window of Bang-bang Control CDA Type-II 94 C SYS-2722 Input and Output Configuration 95 D AUX-0025 Specification 97 | |
| dc.language.iso | en | |
| dc.title | 一個使用迴路濾波器及驅動延遲磁滯控制的D類音頻放大器 | zh_TW |
| dc.title | A Class D Audio Amplifier using Loop Filter and Driver Delay Hysteresis Control | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 99-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 陳昭宏(Jau-Horng Chen),陳伯奇(Poki Chen) | |
| dc.subject.keyword | D類音頻放大器,磁滯控制,總諧波器失真,迴路濾波器, | zh_TW |
| dc.subject.keyword | class D,hysteresis control,THD,loop filter, | en |
| dc.relation.page | 102 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2010-11-18 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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