CMOS雙差動電容感測器研製

Abstract

本論文的目的分成四個部分，1.以HSPICE模擬設計CMOS電容感測器2.將設計的CMOS電容感測器加以佈局並委託由台灣積體電路公司下線3.測試晶片並將其量測結果與設計相比較4.一旦發現錯誤的部分，嘗試修正或改進CMOS電容感測器電路以確認其性能達到要求。 本論文使用國家晶片系統設計中心(NSC Chip Implementation Center, CIC)所提供的台灣積體電路(TSMC)0.35μm Mixed-Signal 2P4M Polycide 3.3/5V的製程，並使用Synopsys 公司所出的Hspice電路模擬軟體[21]與思源公司的laker軟體[20]進行模擬及佈線。

The purposes of this dissertation are four-folds: 1. design the CMOS capacitive sensor with HSPICE simulation, 2. Layout the designed CMOS circuit and tape out it through TSMC company, 3. Test and compare the performances of the CMOS chip with those of original design, 4. once the incorrect performances are found, try to correct or improve the design of the CMOS circuit to ensure the performances of the CMOS chip reaching the design requirement. The dissertation uses 0.35μm Mixed-Signal 2P4M Polycide 3.3/5Vmanufacture process of TSMC which is provided by NSC Chip Implementation Center. Also the Hspice software designed by Synopsys co. is used to simulate the designed circuit, and the Laker software designed by Springsoft co. is adopted to layout the CMOS chip.