以多核心模擬多核心系統中快取記憶體之一致性協定

Abstract

On today’s multicore systems, developing correct and efficient parallel programs can be very challenging. On a shared memory system, inter-thread communications may result in cache contention and cause significant performance degradation which is difficult for application developers to analyze. Simulation tools would be useful for identifying such problems. However, traditional approaches with detailed caches models scale poorly and become impractical for many-core systems. In this thesis, we propose a method to estimate the coherence misses of parallel programs across and within synchronization barriers. We integrated the proposed method into an open-source system-level emulator, COREMU, to evaluate the scalability of simulation. The memory references and the barrier operations in a multi-threaded program are analyzed by our method in parallel to estimate the lower bound and the upper bound for the coherence misses in each parallel region. The results from our experiments show that our approach is useful in finding the source of coherence misses and detecting false sharing data structures in parallel program.