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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 洪士灝(Shih-Hao Hung) | |
| dc.contributor.author | Yu-Wen Huang | en |
| dc.contributor.author | 黃昱文 | zh_TW |
| dc.date.accessioned | 2021-06-15T02:28:17Z | - |
| dc.date.available | 2016-08-26 | |
| dc.date.copyright | 2011-08-26 | |
| dc.date.issued | 2011 | |
| dc.date.submitted | 2011-08-22 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/43775 | - |
| dc.description.abstract | On today’s multicore systems, developing correct and efficient parallel programs can be very challenging. On a shared memory system, inter-thread communications may result in cache contention and cause significant performance degradation which is difficult for application developers to analyze. Simulation tools would be useful for identifying such problems. However, traditional approaches with detailed caches models scale poorly and become impractical for many-core systems.
In this thesis, we propose a method to estimate the coherence misses of parallel programs across and within synchronization barriers. We integrated the proposed method into an open-source system-level emulator, COREMU, to evaluate the scalability of simulation. The memory references and the barrier operations in a multi-threaded program are analyzed by our method in parallel to estimate the lower bound and the upper bound for the coherence misses in each parallel region. The results from our experiments show that our approach is useful in finding the source of coherence misses and detecting false sharing data structures in parallel program. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T02:28:17Z (GMT). No. of bitstreams: 1 ntu-100-R98922067-1.pdf: 3489507 bytes, checksum: e121c1d7431912dec6ac3f0686345a4f (MD5) Previous issue date: 2011 | en |
| dc.description.tableofcontents | Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
中文摘要 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii Abstract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Background and Related Works. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Full-System Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Multicore Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2.1 COREMU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Coherent Cache Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Overview of Fast Cache Coherence Emulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Multi-threaded Cache Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Characterization of Multi-threaded Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 Collecting Parallel Traces on Virtual Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1.1 Generating Parallel Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1.2 Generating Sequential Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 Multi-threaded Coherence Cache Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2.1 Required Communication Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2.2 Optional Communication Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 Evaluation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 Experimental Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2 Experimental Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2.1 Emulation Speed Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2.2 Behaviors of Multi-Threaded Applications on A Many-Core Machine . . . . . . 22 6 Conclusion and Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 | |
| dc.language.iso | en | |
| dc.subject | 快取記憶體 | zh_TW |
| dc.subject | 多核心系統 | zh_TW |
| dc.subject | 虛擬平台 | zh_TW |
| dc.subject | multicore | en |
| dc.subject | coherence miss | en |
| dc.subject | virtual platform | en |
| dc.subject | cache coherence | en |
| dc.title | 以多核心模擬多核心系統中快取記憶體之一致性協定 | zh_TW |
| dc.title | Multicore-on-Multicore Simulation with Emphasis on Cache Coherence Protocols | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 99-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 施吉昇(Chi-Sheng Shih),林風(Phone Lin) | |
| dc.subject.keyword | 虛擬平台,多核心系統,快取記憶體, | zh_TW |
| dc.subject.keyword | virtual platform,multicore,cache coherence,coherence miss, | en |
| dc.relation.page | 31 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2011-08-22 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
| 顯示於系所單位： | 資訊工程學系 | |
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