5-MHz訊號頻寬320-MHz連續時間型三角積分調變器設計

Abstract

隨著3G時代的來臨，從短距離到動輒數百公里的無線電資料與語音傳輸技術不斷地進展，使得無線行動通訊在人類生活中扮演相當重要的角色。由於高輸入動態範圍、高傳輸速率與低功率的需求，使得設計類比數位轉換器（ADCs）也必須達到較高解析度、頻寬與低功率的規格方能滿足這些嚴苛條件外，也可寬鬆無線接收器類比前端（analog front-end）電路部份的設計要求。 本論文在系統層面設計上，著重於電路延遲效應補償的介紹以及時脈抖動的研究；在電路層面設計上，透過仔細地分析、推導與模擬，針對元件非理想效應來取捨評估元件規格。論文主要應用於寬頻分碼多工擷取（WCDMA）無線電通訊上，電路實現在訊號頻寬5-MHz，操作在320-MHz取樣頻率（即過取樣率為32）上之一位元量化三階低通連續時間型三角積分類比數位資料轉換調變器（delta-sigma A/D modulator）。量測結果達56-dB動態範圍（dynamic range）與最大SNR值51.3-dB（相當於8.2-bit有效位元）。利用2P4M 3.3-V台積電CMOS 0.35-μm製程與R-C積分器技術，電流功率消耗13.6-mA。

With the advent of the third-generation (3G) era, wireless technologies on data and sounds transmission ranging from short distances to even hundreds of kilometers at its constant advances have had mobile telecommunications to be a quite important role in human life. Due to the demand for high input dynamic range, data rate, and low power, designing analog-to-digital (A/D) data converters must achieve not only the stringent conditions of higher resolution, higher bandwidth, and low power consumption, but also relax the requirements for the analog front-end parts of radio receivers. This thesis on system-level design focuses on introduction to the compensation of circuit-delayed effects and research to clock jitter; on circuit-level design it shows a better trade-off estimate on specifications through carefully analyzing, deriving out, and simulating the nonideal effects of circuit elements. The proposed implementation of the single-bit third-order low-pass continuous-time delta-sigma analog-to-digital (A/D) modulator can be mainly applied for wideband-code-division-multiple-access (i.e., so-called WCDMA) radio communications with 5-MHz signal bandwidth at sampling frequency of 320-MHz. Experimental results show that a signal-to-noise ratio (SNR) of 51.3dB (i.e., 8.2-bit ENOB) and a dynamic range of 56dB in the 2P4M 3.3-V TSMC CMOS 0.35-μm process with a R-C integrator topology. The measured current consumption is 13.6-mA.