三角積分調變除小數頻率合成器之設計及實作

Abstract

在今日的射頻前級電路中，本地震盪器是一個不可或缺的要件，而設計一個兼具快速的鎖定速度、低相低雜訊和高頻率解析度的頻率合成器也成為一個挑戰。本論文探討MASH的三角積分調變器對於頻率合成器輸出相位雜訊的影響，另外由積體電路實現一個整合性的除小數頻率合成器，並使用MASH 1-1-1 三角積分調變器作為除頻數之調變，一方面藉由打亂除頻器的模數得到較好雜訊抑制，另一方面將雜訊推至較高頻的頻率，而能被鎖相迴路所澸除。此頻率合成器使用0.18μm Mixed-signal 1P6M CMOS製程，可操作於4GHz，模擬的相位雜訊在1MHz處為-115dBc/Hz，並在600MHz的跳頻間距下可達到小於30μm的鎖定時間。

Nowadays, local oscillator is an essential component of the RF front-end. And the design for a frequency synthesizer with agile settling speed, low phase noise and high frequency resolution has become a challenge. The thesis discusses the influence of the MASH Sigma-Delta Modulator (SDM) to the synthesizer output phase noise. The integrated fractional-N frequency synthesizer is implemented with MASH 1-1-1 SDM. On one hand, better fractional and reference spurious suppression is achieved by randomizing the modulus of frequency dividers; on the other hand, the spurious noise is push to higher frequency and will be further filtered out by the PLL. The frequency synthesizer is operated over 4GHz. The simulated phase noise is -115dBc/Hz at 1MHz offset, and the settling time is less than 30μs at 600MHz frequency jumping.