內連線邊緣電容模型及其在探討微元件之吸附電壓之應用

Abstract

本研究目標在提出一能夠準確計算平行板電容的經驗公式，包含二維與三維邊緣電容效應。公式的推導從大量不同幾何尺寸的數值模擬開始，接著取適當的參數對模擬值作曲線回歸，便可以得到二維與三維邊緣電容公式，其準確度與模擬值相比，誤差分別在百分之二與百分之四以內。之後我們利用所提出的二維與三維邊緣電容公式，進行微元件吸附電壓的推導，與文獻之實驗值相比，有相當良好的準確度，證明本研究所提出的公式的確可以應用於微機電元件的設計。最後為了實際驗證本研究所提出之公式，我們使用微機電製程進行了二維與三維邊緣電容的實驗，而二維與三維邊緣電容公式與實驗值相比，誤差分別在百分之三以及百分之五以內。這個高準確度的公式，相較於其他文獻所提出的方式更為便利，且無論在準確度、公式的適用範圍、物理意義等方面，都具有優勢，因此元件設計者可以利用本研究所提出之公式作為參考，只需經由幾何尺寸，無須透過數值模擬或實驗，便可以快速及準確的計算出電容值。

This research aims at developing empirical formulas for parallel-plate capacitor precisely, including two- and three-dimensional fringing capacitance effects. The derivation was started from massive numerical simulations of different geometry, and then we can derive two- and three- dimensional fringing capacitance formulas from choosing appropriate parameters to curve-fitting on results obtained from simulations. The relative errors of two- and three-dimensional fringing capacitance formulas are within 2 and 4 percent comparing with numerical simulations, respectively. Next, we derived the pull-in voltage of micro-devices from these formulas and it shows very high accuracy comparing with experimental data obtained from literature. It demonstrates that the formulas we proposed can apply to the design of microelectromechanical devices. Finally, in order to verify these formulas we proposed actually, we conducted experiment of two- and three-dimensional fringing capacitance by the semiconductor processing. The relative errors of two- and three-dimensional fringing capacitance formulas are within 3 and 5 percent comparing with experimental data, respectively. These high precision empirical formulas are more convenient than other proposed methods, and the accuracy, the applicative range, and the physical meaning are better, too. Therefore, by these high precision formulas, designers can easily evaluate the capacitance through the geometry in a few seconds.