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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電子工程學研究所
Please use this identifier to cite or link to this item: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/36703
Title: 低頻帶超寬頻系統之互補式金氧半射頻前端電路設計
CMOS RF Front-End Circuit Design for Low-Band Ultra-Wideband Systems
Authors: Chang-Yu Chen
陳昶聿
Advisor: 汪重光(Chorng-Kuang Wang)
Keyword: 超寬頻,射頻前端,低雜訊放大器,混頻器,
ultra-wideband,RF front-end,low noise amplifier,mixer,
Publication Year : 2005
Degree: 碩士
Abstract: 近年來,由於多媒體應用的迅速發展,在通訊系統中的高速度和高傳輸率已成為極重要的課題。在如此殷切的需求之下,也促使了下一代無線科技的發展與誕生—超寬頻系統。而今日先進的互補式金氧半製程除仍具有低成本與低功率損耗之優點外,也使整合超寬頻接收機於單晶片上的目標得以實現。
在這份論文中,主要著重於低頻帶超寬頻系統之射頻前端電路設計。接收機中的兩個關鍵元件將會被詳細的討論與說明。首先是3~5GHz 寬頻低雜訊放大器之設計,其採用了頻帶交錯的技巧來達到寬頻的特性。在低雜訊放大器中的寬頻匹配問題乃使用共閘極電阻性回授式的架構來解決。另一個設計為寬頻混頻器,其利用了並-並式的回授來提高頻寬。最後,一個適用於超寬頻系統的完整接收機將會被設計並模擬。在1.8伏特的電源供應之下,整個接收機的前端電路共消耗33毫瓦,且晶片面積約為1.37 x 1.05 mm2。所有的電路都經由佈局後模擬驗証,同時前一個電路的量測結果也會一併呈現。
Recently, due to the rapid growth of multimedia applications, high speed and high date rate in communication systems has become more and more important. Under this urgent demand, it accelerates the development and birth of the next-generation of wireless technology—ultra-wideband (UWB) systems. Nowadays, because of its advantage of low cost and low power dissipation, advanced CMOS process make it possible to integrate a UWB receiver into a single chip for VLSI implementation.
In this thesis, the primary target is the RF front end design for low-band UWB applications. Two key components of the receiver are discussed and presented. The first design is a 3~5 GHz wideband low noise amplifier, which adopts stagger technique to achieve a wideband characteristic. The wideband matching problem of LNA is solved by using common gate resistive feedback (CGRF) architecture. The second design is a wideband mixer, which utilizes the shunt-shunt feedback to enhance its bandwidth. Finally, the complete receiver chain for UWB applications which contains a LNA and two mixers is designed and simulated. The total power consumption of the receiver front-end circuit is 33mW under 1.8V supply voltage and chip area is about 1.37 x 1.05 mm2. All the circuits are verified from post-layout simulation. The former is presented with measurement results.
URI: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/36703
Fulltext Rights: 有償授權
Appears in Collections:電子工程學研究所

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