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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電機工程學系
Please use this identifier to cite or link to this item: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/33461
Title: 以SystemC為基礎的嵌入式作業系統模擬器
An RTOS-Centric Simulator in SystemC for Embedded System
Authors: Chih-Yun Liu
劉志昀
Advisor: 陳少傑
Keyword: 嵌入式,模擬器,作業系統,
Embedded System,SystemC,Simulator,
Publication Year : 2006
Degree: 碩士
Abstract: 此論文提出一個針對嵌入式系統應用層的軟體模擬系統。此模擬系統是使用目前最流行於電子系統級(ESL)的硬體模型建構語言SystemC來設計。
本文中我們設計的軟體模擬系統提供一個泛用的作業系統模型。這模型支援一般嵌入式即時系統常用的各種元件如執行緒(Thread),中斷處理常式(ISR) , 號誌(Semaphore),事件旗號(Event)和訊息序列(Message)。 整個系統採用物件導向技術來設計,使用者可以很容易加以擴張其功能。
使用者可以很容易利用此系統的應用程式介面來建立自己想要模擬的軟體系統。另外這系統可以很容易的與SystemC建構的硬體模型來連結。透過軟硬體模型的共同模擬,很容易透過觀察整個系統的內部行為來對系統進行驗證分析。
In this Thesis, we propose the design of a Real-Time Operating System (RTOS) centric simulator for embedded systems. This design is based on the SystemC language, which is the most popular system and hardware modeling language used in the Electronic System Level (ESL) design. This methodology facilitates integrating our simulator with other SystemC-based hardware models.
The proposed simulator provides an abstract layer of generic RTOS model, which supports functions such as threads, ISR (Interrupt Service Routine), semaphores, event flags, and message queues. The whole design is implemented using an object-oriented design methodology such that users can extend the functions of this simulator in an easy way.
The application layer of software can be integrated with this simulator using the supported general RTOS service APIs. The embedded system developers can easily build a simulation model containing software and hardware components. The behavior of software can be investigated and verified from the co-simulation of hardware and software.
URI: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/33461
Fulltext Rights: 有償授權
Appears in Collections:電機工程學系

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