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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳少傑 | |
| dc.contributor.author | Chih-Yun Liu | en |
| dc.contributor.author | 劉志昀 | zh_TW |
| dc.date.accessioned | 2021-06-13T04:41:48Z | - |
| dc.date.available | 2006-07-25 | |
| dc.date.copyright | 2006-07-25 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-07-17 | |
| dc.identifier.citation | [1] G. Moore, “Cramming More Components Onto Integrated Circuits,” Electronics, Vol. 38, pp. 114–117, April 1965.
[2] 上田勝彥, “松下電器の産学連携取組み概要及びシステムＬＳＩ設計技術から見た産学連携の課題,” in Lecture Materials of STARC Symposium 2005, September 2005, Available at http://www.starc.jp/download/sympo2005-j.html. [3] “Functional Specification for SystemC 2.0,” and “SystemC User's Guide,” Available at http://www.systemc.org. [4] G. Moretti, “The Search for the Perfect Language,” EDN Magazine, pp. 40-50, February 2004. [5] D.C. Black and J. Donovan, SystemC: From The Ground Up, Kluwer Academic Publishers, 2004. [6] J. Chevalier, O. Benny, M. Rondonneau, G. Bois, E.-M. Aboulhamid, and J.-F. Boyer, “SPACE: A Hardware/Software SystemC Modeling Platform including an RTOS,” in Proceedings of Forum on Design Languages (FDL'03), Frankfurt, pp. 704-715, September 2003. [7] D. Keppel, Tools and Techniques for Building Fast Portable Thread Packages, Technical Report UWCSE-93-05-06, Computer Science and Engineering, Univ. of Washington, May 1993. [8] L. Semeria and A. Ghosh, “Methodology for Hardware/Software Co-verification in C/C++,” in Proceedings of Asia and South Pacific Design Automation Conference 2000 (ASP-DAC'00), pp. 405-408, 2000. [9] M.K. Chung and C.M. Kyung, “Improvement of Compiled Instruction Set Simulator by Increasing Flexibility and Reducing Compile Time,” in Proceedings of 15th IEEE International Workshop on Rapid System Prototyping (RSP'04), pp. 38-44, 2004. [10] B. Roslund and P. Andersson, “A Flexible Technique for OS-Support in Instruction Level Simulators,” in Proceedings of the 27th Annual Simulation Symposium, pp.134 – 141, 1994. [11] WindRiver Systems Inc., “VxWorks for General Purpose Platform,” Available at http://www.windriver.com. [12] S. Honda, T. Wakabayashi, H. Tomiyama, and H. Takada, 'RTOS-Centric Hardware/Software Cosimulator for Embedded System Design,' in Proceedings of International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'04), pp. 158-163, September 2004. [13] H. Takada and K. Sakamura, “μITRON for Small-Scale Embedded Systems,” IEEE Microelectronics, Vol. 15, No. 6, pp. 46-54, December 1995. [14] μITRON 4.0 Specification, Available at http://www.tron.org. [15] S. Yoo, G. Nicolescu, L. Gauthier, and A.A. Jerraya, “Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design,” in Proceedings of the Conference on Design, Automation and Test in Europe (DATE'02), pp. 620-627, 2002. [16] S. Yoo, I. Bacivarov, A. Bouchhima, Y. Paviot, and A.A. Jerraya, “Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer,” in Proceedings of the Conference on Design, Automation and Test in Europe (DATE'03), pp. 10550-10555, 2003. [17] H.M. AbdElSalam, S. Kobayashi, K. Sakanushi, Y. Takeuchi, and M. Imai: “Towards a Higher Level of Abstraction in Hardware/Software Co-Simulation,” in Proceedings of the 24th International Conference on Distributed Computing Systems Workshops (ICDCSW'04), pp. 824-830, 2004. [18] P. Hastono, S. Klaus, and S.A. Huss, “An Integrated SystemC Framework for Real-Time Scheduling Assessments on System Level,” in Work-In-Progress Proceedings of the 25th IEEE International Real-Time Systems Symposium (RTSS'04), pp. 8-11, 2004. [19] Z. He, A. Mok, and C. Peng, “Timed RTOS Modeling for Embedded System Design,” in Proceedings of the 11th IEEE Real Time and Embedded Technology and Applications Symposium (RTAS'05), pp. 448-457, 2005. [20] H.M. AbdElSalam, K. Sakanushi, Y. Takeuchi, and M. Imai, “RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC,” in Proceedings of the Conference on Design, Automation and Test in Europe (DATE '05), Vol. 1, pp. 554-559, 2005. [21] H.M. AbdElSalam, K. Sakanushi, Y. Takeuchi, and M. Imai, “Virtual Prototyping of T-Engine Systems Using RTOS Centric Cosimulation,” in Proceedings of the Third International Conference on Information and Communications Technology (ICICT'05), pp. 171 – 191, December 2005. [22] Y. Yi, D. Kim, and S. Ha, “Virtual Synchronization Technique with OS modeling for Fast and Time-accurate Cosimulation,” in Proceedings of International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'03), pp. 1-6, October 2003. [23] M. Brett, B. Gerstenberg, C. Herberg, G. Shavit, and H. Liondas, “Video Processing for Single-Chip DVB Decoder,” IEEE Transactions on Consumer Electronics, Vol. 47, Issue 3, pp. 385 – 393, August 2001. [24] J.W.S. Liu, Real-Time Systems, Prentice Hall, 2000. [25] K. Ghosh, B. Mukherjee, and K. Schwan, A Survey of Real-Time Operating Systems, Technical Report No. GIT-CC-93/18, College of Computing, Georgia Inst. of Technology, U.S.A., February 1994. [26] A. Coben and M. Woodring, Win32 Multithreaded Programming, O'Reilly & Associate Inc., 1997 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/33461 | - |
| dc.description.abstract | 此論文提出一個針對嵌入式系統應用層的軟體模擬系統。此模擬系統是使用目前最流行於電子系統級(ESL)的硬體模型建構語言SystemC來設計。
本文中我們設計的軟體模擬系統提供一個泛用的作業系統模型。這模型支援一般嵌入式即時系統常用的各種元件如執行緒(Thread)，中斷處理常式(ISR) , 號誌(Semaphore)，事件旗號(Event)和訊息序列(Message)。 整個系統採用物件導向技術來設計，使用者可以很容易加以擴張其功能。 使用者可以很容易利用此系統的應用程式介面來建立自己想要模擬的軟體系統。另外這系統可以很容易的與SystemC建構的硬體模型來連結。透過軟硬體模型的共同模擬，很容易透過觀察整個系統的內部行為來對系統進行驗證分析。 | zh_TW |
| dc.description.abstract | In this Thesis, we propose the design of a Real-Time Operating System (RTOS) centric simulator for embedded systems. This design is based on the SystemC language, which is the most popular system and hardware modeling language used in the Electronic System Level (ESL) design. This methodology facilitates integrating our simulator with other SystemC-based hardware models.
The proposed simulator provides an abstract layer of generic RTOS model, which supports functions such as threads, ISR (Interrupt Service Routine), semaphores, event flags, and message queues. The whole design is implemented using an object-oriented design methodology such that users can extend the functions of this simulator in an easy way. The application layer of software can be integrated with this simulator using the supported general RTOS service APIs. The embedded system developers can easily build a simulation model containing software and hardware components. The behavior of software can be investigated and verified from the co-simulation of hardware and software. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T04:41:48Z (GMT). No. of bitstreams: 1 ntu-95-P93921002-1.pdf: 1349274 bytes, checksum: 81a1f106f03cc072bf990fcbcbaa7815 (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | ABSTRACT i
LIST OF FIGURES v LIST OF TABLES vii 1. INTRODUCTION 1 1.1 Motivation 1 1.2 Contribution 2 1.3 Thesis Organization 3 2. RELATED WORK 5 2.1 SystemC Introduction 5 2.1.1 SystemC Language Features 5 2.1.2 SystemC Simulation Kernel 7 2.1.3 Problem for Software Simulation in SystemC 7 2.2 Software Simulation 8 2.2.1 ISS Based Simulation 8 2.2.2 Native Simulation 9 2.2.3 RTOS Based Simulation 10 2.3 Summary 12 2.3.1 Issues in Previous Work 12 2.3.2 Direction of our Work 13 3. GOS: AN RTOS CENTRIC SIMULATOR 15 3.1 Design Specification of the Simulator 15 3.2 Simulation Model 17 3.2.1 Thread Modeling 17 3.2.2 Modeling of Preemption and Synchronization 19 3.3 Architecture of the GOS Simulator 21 3.4 Design of the GOS Simulator 23 3.4.1 The Base Class of GOS Objects 24 3.4.2 Task and ISR 25 3.4.3 Synchronization and IPC Components 28 3.4.4 GOS Kernel Design 30 3.4.5 Resource Management and Bus Functional Model 35 3.5 Simulation API 36 3.5.1 Implementation of GOS Service API 37 3.5.2 Timing Annotation 38 3.6 Debugging and Signal Tracing 39 4. EVALUATION OF THE GOS SIMULATOR 43 4.1 Implementation of GOS Applications 43 4.2 Functional Verification 44 4.3 Design Example 46 5. CONCLUSION 49 REFERENCE 51 | |
| dc.language.iso | en | |
| dc.subject | 作業系統 | zh_TW |
| dc.subject | 嵌入式 | zh_TW |
| dc.subject | 模擬器 | zh_TW |
| dc.subject | Simulator | en |
| dc.subject | SystemC | en |
| dc.subject | Embedded System | en |
| dc.title | 以SystemC為基礎的嵌入式作業系統模擬器 | zh_TW |
| dc.title | An RTOS-Centric Simulator in SystemC for Embedded System | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 94-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 王凡,黃文良,熊博安,林風 | |
| dc.subject.keyword | 嵌入式,模擬器,作業系統, | zh_TW |
| dc.subject.keyword | Embedded System,SystemC,Simulator, | en |
| dc.relation.page | 53 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2006-07-19 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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