以設計分析與驗證為目的之暫存器轉移層快速合成法

Abstract

In this thesis, we proposed a quick register transfer level(RTL) front end for design analysis and verification. Our front end consists of three parts: (1) an RTL parser that supports most of the synthesizable Verilog subset and various library formats; (2) an elaborating process that generates control data flow graph(CDFG) and can be used for design intent extraction and (3) a logic synthesizer that translates the design into a word-level netlist and writes out a structural Verilog file. We have been able to read in several designs from other design teams and have verified the correctness of our front end by the Cadence Conformal Logic Equivalence Checker(LEC). With the word-level data structure and high-level design intent extraction at hand, we will be able to conduct more research on the design debugging and verification in the future.