請用此 Handle URI 來引用此文件：
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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃鐘揚(Chung-Yang Huang) | |
| dc.contributor.author | Chun-Fu Huang | en |
| dc.contributor.author | 黃俊輔 | zh_TW |
| dc.date.accessioned | 2021-06-13T04:33:26Z | - |
| dc.date.available | 2006-07-21 | |
| dc.date.copyright | 2006-07-21 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-07-19 | |
| dc.identifier.citation | [1] B. Bailey and D. Gajski. RTL semantics and methodology. In International
Symposium on Syntems Synthesis, pages 69–74, 2001. [2] Douglas J. Smith. HDL Chip Design. Doone Publications, 1996. [3] E. McCluskey. Minimization of Boolean Functions. In The Bell Syntem Technical Journal, volume 35, pages 1417–1444, 1956. [4] Giovanni De Micheli. Synthesis and Optimization of Digital Circuits. McGraw- Hill Inc., 1994. [5] Joan Daemen, Vincent Rijmen. AES: Advanced Encryption Standard. http://csrc.nist.gov/CryptoToolkit/aes/rijndael/. [6] P. Brisk, F. Dabiri, R. Jafari, M. Sarrafzadeh. Optimal register sharing for high-level synthesis of SSA form programs. In IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, volume 25, pages 772–779, 2006. [7] P. Jamieson, J. Rose. A Verilog RTL synthesis tool for heterogeneous FPGAs. In Field-Programmable Logic and Applications, pages 305–310, 2005. [8] P. McGeer, J. Sanghavi, R. Brayton, A. Sangiovanni-Vincentelli. ESPRESSOSIGNATURES: A New Exact Minimizer for Logic Functions. In Design Automation Conference, pages 618–621, 1993. [9] R. Brayton, G. Hachtel, A. Sangiovanni-Vincentelli. Multilevel Logic Synthesis. In IEEE Proceedings, volume 78, pages 264–300, 1990. [10] Ravi Namballa, N.Ranganathan and Abdel Ejnioui. Control and Data Flow Graph Extraction for High-Level Synthesis. In IEEE Annual Symposium on VLSI, pages 187–192, 2004. [11] Samir Palnitkar. Verilog HDL. Prentice Hall, 1994. [12] Schliebusch, O. Chattopadhyay, A. Leupers, R. Ascheid, G. Meyr, H. Steinert, M. Braun, G. Nohl, A. Integrated Signal Process. Syst., Aachen Univ. of Technol., Germany. RTL processor synthesis for architecture exploration and implementation. In Design, Automation and Test in Europe Conference and Exhibition, pages 156–160, 2004. [13] Shuqing Zhao, Daniel D. Gajski. Defining an enhanced RTL Semantics. In Design, Automation and Test in Europe, pages 548–553, 2005. [14] Srinivas Devadas, Abhijit Ghosh and Kurt Keutzer. Logic Synthesis. McGraw- Hill Inc., 1994. [15] Stephen Williams. Icarus Verilog, 2001. [16] VIS Group. VIS: Verification Interacting with Synthesis. In International Conference on Computer Aided Verification, pages 428–432, 1996. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/33298 | - |
| dc.description.abstract | In this thesis, we proposed a quick register transfer level(RTL) front end for design analysis and verification. Our front end consists of three parts: (1) an RTL parser that supports most of the synthesizable Verilog subset and various library formats; (2) an elaborating process that generates control data flow graph(CDFG) and can be used for design intent extraction and (3) a logic synthesizer that translates the design into a word-level netlist and writes out a structural Verilog file. We have been able to read in several designs from other design teams and have verified the correctness of our front end by the Cadence Conformal Logic Equivalence Checker(LEC). With the word-level data structure and high-level design intent extraction at hand, we will be able to conduct more research on the design debugging and verification in the future. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T04:33:26Z (GMT). No. of bitstreams: 1 ntu-95-R93921109-1.pdf: 1289399 bytes, checksum: bf0a4c7cddfd6d489d2c1850bbb307df (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | 1 Introduction 8
1.1 Problem Description . . . . . . . . . . . . . . . . . 8 1.2 Previous Work . . . . . . . . . . . . . . . . . . . . 8 1.2.1 VIS . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.2 Icarus Verilog. . . . . . . . . . . . . . . . . . . 9 1.3 Our Contribution. . . . . . . . . . . . . . . . . . . 10 1.3.1 A Powerful Front End. . . . . . . . . . . . . . . . 10 1.3.2 Design Analysis . . . . . . . . . . . . . . . . . . 10 1.3.3 Easy Extension. . . . . . . . . . . . . . . . . . . 10 2 The Basics of RTL Synthesis 11 2.1 Synthesis Flow Overview . . . . . . . . . . . . . . . 11 2.2 Data Structures. . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.1 HDL Parser. . . . . . . . . . . . . . . . . . . . . 11 2.2.2 Circuit . . . . . . . . . . . . . . . . . . . . . . 13 2.3 Modeling Issues . . . . . . . . . . . . . . . . . . . 14 3 Realization 19 3.1 Overview of The Framework . . . . . . . . . . . . . . 19 3.2 Control Flow Synthesis. . . . . . . . . . . . . . . . 20 3.2.1 Decription. . . . . . . . . . . . . . . . . . . . . 20 3.2.2 Statements without Condition. . . . . . . . . . . . 21 3.2.3 Statements under If Condition . . . . . . . . . . . 21 3.2.4 Statements under Case Condition . . . . . . . . . . 22 3.2.5 Statements under For Condition. . . . . . . . . . . 24 3.2.6 Mux v.s. Latch. . . . . . . . . . . . . . . . . . . 24 3.2.7 Carry-out Problemin Arithmetic Operations . . . . . 25 3.3 Always Statement. . . . . . . . . . . . . . . . . . . 26 3.3.1 Sequential Block. . . . . . . . . . . . . . . . . . 26 3.3.2 Combinational Block . . . . . . . . . . . . . . . . 27 3.3.3 Blocking and Non-blocking Assignments . . . . . . . 27 3.4 Continuous Assignments. . . . . . . . . . . . . . . . 27 3.5 Function. . . . . . . . . . . . . . . . . . . . . . . 28 3.5.1 Problem Description . . . . . . . . . . . . . . . . 28 3.5.2 Statement Ordering Problem in Function. . . . . . . 29 3.6 Bus Overlap Problem . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.6.1 Problem Description . . . . . . . . . . . . . . . . 30 3.6.2 Bus Overlap Situations . . . . . . . . . . . .. . . 30 3.6.3 Split Original Value . . . . . . . . . . . . . . .. 33 3.7 Parameter Overload Problem . . . . . . . . . . . . . .34 3.7.1 Problem Description . . . . . . . . . . . . . . . . 34 3.7.2 Module Instantiation with Parameter Overloading . . 35 3.7.3 Dynamic Overloading . . . . . . . . . . . . . . . . 35 3.7.4 Static Overloading . . . . . . . . . . . . . . . . 36 3.8 Tri-state Extraction . . . . . . . . . . . . . . . . . . . . . . . .37 4 Verication 38 4.1 Writing Structural Verilog Output . . . . . . . . . . 38 4.2 Experimental Setup . . . . . . . . . . . . . . . . . 43 4.3 Experimental Result . . . . . . . . .. . . . . . . . 47 4.3.1 AES . . . . . . . . . . . . . . . . . . . . . . . . 47 4.3.2 SDRAMController . . . . . . . . . . . . . . . . . . 50 4.3.3 Result Discussion . . . . . . . . . . . . . . . . . 53 5 Conclusion and Future Work 57 References 58 Appendices 60 A User’sManual 60 B Verilog BNF 61 | |
| dc.language.iso | en | |
| dc.title | 以設計分析與驗證為目的之暫存器轉移層快速合成法 | zh_TW |
| dc.title | Quick RTL Synthesis for Design Analysis and Verification | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 94-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李建模(Chien-Mo Li),黃錫瑜(Shi-Yu Huang) | |
| dc.subject.keyword | 邏輯合成,設計分析, | zh_TW |
| dc.subject.keyword | logic synthesis,design analysis, | en |
| dc.relation.page | 71 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2006-07-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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