Please use this identifier to cite or link to this item:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/32781
Title: | 積體電路多時脈路徑之自動化查驗條件產生器 Automatic Multi-Cycle Path Assertion Property Generation in VLSI Designs |
Authors: | Shih-Kuei Wei 魏士貴 |
Advisor: | 黃鐘揚 |
Keyword: | 積體電路,多時脈路徑,自動化,查驗條件, VLSI,Multi-Cycle Path,Assertion,Property, |
Publication Year : | 2006 |
Degree: | 碩士 |
Abstract: | In this thesis, we proposed an effective method to verify the multi-cycle paths in a gate-level design with the SDC (Synopsis Design Constraint) timing constraints in the design setup file. We analyzed the usage of multi-cycle paths, and summarized it into several types of multi-cycle path structures. Based on the different types of multi-cycle path structures, we generated the assertion properties for them in the format of SystemVerilog assertions. The assertion properties define the behavior of the multi-cycle paths in the design, and they can be used as checkers in the dynamic simulation tool to verify the multi-cycle path timing constraints. In the experiment result, we showed some examples to illustrate the procedure of our approach. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/32781 |
Fulltext Rights: | 有償授權 |
Appears in Collections: | 電子工程學研究所 |
Files in This Item:
File | Size | Format | |
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ntu-95-1.pdf Restricted Access | 1.79 MB | Adobe PDF |
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