請用此 Handle URI 來引用此文件:
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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 黃鐘揚 | |
dc.contributor.author | Shih-Kuei Wei | en |
dc.contributor.author | 魏士貴 | zh_TW |
dc.date.accessioned | 2021-06-13T04:15:26Z | - |
dc.date.available | 2006-07-27 | |
dc.date.copyright | 2006-07-27 | |
dc.date.issued | 2006 | |
dc.date.submitted | 2006-07-24 | |
dc.identifier.citation | [1] Hiroyuki Higuchi, “An Implication-based Method to Detect Multi-Cycle Paths in Large Sequential Circuits”. 39th ACM/IEEE Design Automation Conference, June 2002, p.164-169.
[2] Hiroyuki Higuchi and Yusuke Matsunaga, “Enhancing the performance of multi-cycle path analysis in an industrial setting”, ASP-DAC 2004: p192-p197 [3] Encounter™ Conformal® Constraint Designer reference manual, product version 6.1, May 2006. [4] SystemVerilog 3.1a Language Reference Manual, “Accellera’s Extensions to Verilog®”. [5] FishTail Design Automation, “Automatically Generating Golden Timing Constraints”. [6] Kazuhiro Nakamura, “Studies on Multi-Cycle Paths of Sequential Circuits”, 2001. [7] Accellerar, “SVA Technology and User Experience”. [8] Kai Yang, Kwang-Ting Cheng, “Efficient Identification of Efficient Identification of Multi Multi-Cycle False Path Cycle False Path”,Department of Electrical and Computer Engineering University of California, Santa Barbara. [9] Synopsys, PrimeTime Commands, Version 2004.12, December 2004. [10] Tai Ly, Neil Hand, Chris Ka-kei Kwok, “Formally Verifying Clock Domain Crossing Jitter Using Assertion-Based Verification”. [11] Jay Littlefield, Prakash Narain and Subash Sundaresan, Real Intent, Inc. Thomas Anderson, Technical Marketing Consultant , “Designing a Safe Multi-Clock Chip with Clock Intent Verification”. [12] Tsachy Kapschitz, Ran Ginosar, Richard Newton, “Verifying Synchronization in Multi-Clock Domain SoC”. [13] Ankur Agiwal and Montek Singh, “An Architecture and a Wrapper Synthesis Approach for Multi-Clock Latency-Insensitive Systems”, 2005 IEEE. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/32781 | - |
dc.description.abstract | In this thesis, we proposed an effective method to verify the multi-cycle paths in a gate-level design with the SDC (Synopsis Design Constraint) timing constraints in the design setup file. We analyzed the usage of multi-cycle paths, and summarized it into several types of multi-cycle path structures. Based on the different types of multi-cycle path structures, we generated the assertion properties for them in the format of SystemVerilog assertions. The assertion properties define the behavior of the multi-cycle paths in the design, and they can be used as checkers in the dynamic simulation tool to verify the multi-cycle path timing constraints. In the experiment result, we showed some examples to illustrate the procedure of our approach. | en |
dc.description.provenance | Made available in DSpace on 2021-06-13T04:15:26Z (GMT). No. of bitstreams: 1 ntu-95-R93943113-1.pdf: 1831976 bytes, checksum: 9fbe8c6c308d10b3ec06331f4ad93fe2 (MD5) Previous issue date: 2006 | en |
dc.description.tableofcontents | ABSTRACT i
List of Contents ii List of Figures iv Chapter 1 Introduction 1 1.1 Multi-Cycle Path 2 1.2 Related Previous Work 2 1.2.1 Synopsys PrimeTime 2 1.2.2 Cadence Encounter™ Conformal® Constraint Designer 3 1.2.3 An Implication Based Method 4 1.3 Proposed approach 5 Chapter 2 Preliminary 8 2.2 SDC in Design Setup File 13 2.3 Multi-Cycle Path Structures in Designs 15 Chapter 3 Multi Cycle Path Assertion Property Generation 22 3.1 Feedback Loop Style MCP 22 3.2 EDFF Style MCP 40 3.3 Clock Controlling Style MCP 46 Chapter 4 Experimental Result 58 4.1 Case Study 1:Feedback Loop Style MCP 58 4.2 Case Study 2:EDFF Style MCP 60 4.3 Case Study 3:Clock Controlling Style MCP 62 Chapter 5 Conclusion and Future Work 65 Chapter 6 Reference 66 | |
dc.language.iso | en | |
dc.title | 積體電路多時脈路徑之自動化查驗條件產生器 | zh_TW |
dc.title | Automatic Multi-Cycle Path Assertion Property Generation in VLSI Designs | en |
dc.type | Thesis | |
dc.date.schoolyear | 94-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 李建模,張耀文,黃世安 | |
dc.subject.keyword | 積體電路,多時脈路徑,自動化,查驗條件, | zh_TW |
dc.subject.keyword | VLSI,Multi-Cycle Path,Assertion,Property, | en |
dc.relation.page | 67 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2006-07-25 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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