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Title: | 支援全速延遲測試之IEEE 1500標準測試封套設計與驗證測試方法 IEEE 1500 Compatible Test Wrapper Design and Validation for At-Speed Delay Testing |
Authors: | Tsung-Ping Kao 高琮評 |
Advisor: | 李建模 |
Keyword: | 全速,延遲,驗證,測試,系統晶片, IEEE 1500,Validation,At-Speed,Delay,Testing, |
Publication Year : | 2007 |
Degree: | 碩士 |
Abstract: | 本論文在延遲錯誤測試方面,我們提出了兩種延遲錯誤測試方法,稱之為G1P2以及G2P2。G1P2為一省測試面積及測試時間的延遲錯誤測試方法,而G2P2為一全速(At-Speed)延遲錯誤測試方法。我們的延遲錯誤測試方法或許需增加若干之測試點,我們亦有提出測試點之選擇方法。我們也實作了配合IEEE 1500標準測試封套的自動化系統晶片(System on Chip, SoC) 驗證軟體。透過此工具自動產生之驗證用測試平臺(TestBench)可支援單一黏著性錯誤模型(Single stuck-at fault model),以及延遲錯誤模型(Delay fault model)的測試。本論文亦依IEEE 1450.6標準核心測試語言,實作了核心測試語言產生器(CTL Generator),產生所需之系統晶片測試圖樣(Test Patterns)。 In this thesis, two delay fault test methods are proposed,G1P2 and G2P2. G1P2 is a delay fault test method which may save test area and test time. G2P2 is a precise At-Speed delay fault test method. Our delay fault test methods would need some test points. A test point selection method is presented.An automatic testbench generator for testing a SoC(System on Chip) with IEEE 1500 wrapped cores is implemented. The generated testbench is flexible for testing the SoC in either single stuck-at fault model or delay fault model test applications. A CTL generator for generating SoC test patterns is also implemented. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/31213 |
Fulltext Rights: | 有償授權 |
Appears in Collections: | 電子工程學研究所 |
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ntu-96-1.pdf Restricted Access | 849.75 kB | Adobe PDF |
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