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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 李建模 | |
dc.contributor.author | Tsung-Ping Kao | en |
dc.contributor.author | 高琮評 | zh_TW |
dc.date.accessioned | 2021-06-13T02:36:12Z | - |
dc.date.available | 2007-01-24 | |
dc.date.copyright | 2007-01-24 | |
dc.date.issued | 2007 | |
dc.date.submitted | 2007-01-18 | |
dc.identifier.citation | [Adham 99]S. Adham et al. , “Preliminary Outline of IEEE P1500 Scalable Architecture for Testing Embedded Cores” ,Proc. IEEE VLSI Test Symposium (VTS), Dana Point, CA, April 1999, pp.483–488.
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Chakrabarty, 'Defect-oriented and time-constrained wafer-level test length selection for core-based SOCs', Proc. IEEE International Test Conference, 2006. [Chiu 05] Hao-Hsuan Chiu, Po-Lin Chen, Chung-Yi Li, and Tsin-Yuan Chang“A Delay Test Wrapper Design on Core-Based System-on-Chip”Dept. Of Electrical Engineering, National Tsing Hua Univ., Hsinchu, Taiwan 300,Proc. 16th VLSI/CAD P2-62. [Dahbura 89] A. T. Dahbura , M. Uyar , and C. W. Yau , “An optimal test sequence for the JTAG/IEEE P1149.1 test access port controller”, Proc. IEEE International Test Conf. (ITC), 1989,pp. 55–62. [DaSilva 03]F. DaSilva , Y. Zorian , L. Whetsel , K. Arabi , R. Kapur , “Overview of the IEEE P1500 Standard” , Proc. IEEE International Test Conf. (ITC) , pp. 887-889, 2003. [Devtaprasanna 05] N. Devtaprasanna , A. Gunda , P. Krishnamurthy, S.M. Reddy and I. Pomeranz , “METHODS FOR IMPROVING TRANSITION DELAY FAULT COVERAGE USING BROADSIDE TESTS” , Proc. International Test Conference, 2005, pp. 256-265. [Eric 99] Eric Jan Marinissen, Yervant Zorian, Rohit Kapur, Tony Taylor, and Lee Whetsel, “Towards a standard for Embedded Core Test: An Example,” Proc. IEEE International Test Conference(ITC), 1999, pages 616-627. [IEEE 1149.1]” IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture”, IEEE Std 1149.1,1990. [IEEE 1450.6] “IEEE Standard Test Interface Language (STIL) for Digital Test Vector Data-Core Test Language (CTL)” IEEE Std 1450.6,2005. [IEEE 1500] “IEEE Standard Testability Method for Embedded Core-based Integrated Circuits”IEEE Std 1500,2005. [ISCAS Web Site] http://www.eecs.umich.edu/~jhayes/iscas.restore/benchmark.html [Kapur 01] Rohit Kapur , Maurice Lousberg , Tony Taylor , Brion Keller , Paul Reuter , Douglas Kay , ”CTL the language for describing Core-Base testing”, Proc. IEEE International Test Conf. (ITC), 2001 , Page: 131. [Lee 00]K.-J. Lee ,C.-I. Huang , “A Hierarchical Test Control Architecture for Core Based Design,” Proc. 9th IEEE Asian Test Symp.(ATS), IEEE CS Press, Los Alamitos, Calif.,2000, pp. 248-253. [Li 02] Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen,Chih-Pin Su,Cheng-Wen Wu,Chuang Cheng,Shao-I Chen,Chi-Yi Hwang,Hsiao-Ping Lin“A HIERARCHICAL TEST METHODOLOGY FOR SYSTEMS ON CHIP” ,Proc. IEEE International Test Conference , 2002, PP.69 – 81 [Li 04] James C.-M. Li, “A Design for Testability Technique for Low Power Delay Fault Testing” , Proc. IEICE Trans. on Electronics, Vol. E87-C, No. 4, April, 2004, pp. 621-628. [Li 05] J. -F. Li and C. -S. Wu , “Design-for-Testability and Testing of P1500 Test Wrapper”, Proc. VLSI Design/CAD symposium, pp. 254-257, 2005. [Liao 05] Yu-Te Liao , “A Two-Level Test Data Compression and Test Time Reduction Technique for SOC” , National Taiwan Univ. Master thesis, 2005. [MARINISSEN 02]Erik Jan Marinissen , Rohit Kapur , Maurice Lousberg , Teresa Mclaurin , Mike Ricchetti , Yervant Zorian , “On IEEE P1500’s Standard for Embedded Core Test” , Proc. Journal of Electronic Testing: Theory and Applications (JETTA), Volume 18, August 2002, pp. 365-383 [Mitra 02]S. Mitra, E. J. McCluskey , and S. Makar , “Design for testability and testing of IEEE 1149.1 TAP controller”, Proc. IEEE VLSI Test symposium (VTS), pp. 247-252, 2002. [Niklas 03] ' An Extensible SAT-solver ' Niklas Eén, Niklas Sörensson, SAT 2003 [Poirier 93] Poirier . C , “IEEE P1149.5 to 1149.1 data and protocol conversion”, Proc. IEEE International Test Conference, 1993, pp. 527 - 535. [Park 99] IEEE Computer Society , “IEEE Standard Test Interface Language (STIL) for Digital Test Vector Data” , Language Manual – IEEE Std.1450.0,1999. IEEE New York, September 1999. [Taylor 96] Tony Taylor ,Gregory A.Maston ,” Standard Test Interface Language(STIL),A NEW Language for Pattern and Waveforms” , Proc. IEEE International Test Conference(ITC) , 1996 ,pp. 565 - 570. [Taylor 98]Tony Taylor,“Standard Test Interface Language(STIL),Extending the Standard” , Proc. IEEE International Test Conference(ITC) , 1998 ,pp. 962 - 970. [Whetsel 97]L. Whetsel , “An IEEE 1149.1 Base Test Access Architecture for ICs with EmbeddedCores” , Proc. IEEE International Test Conference(ITC), IEEE CS Press, Los Alamitos, Calif., 1997, pp. 69-78. [Wang 05]Shin-Moe Wang, Chih-Yen Lo, Chen-Hsing Wang, and Cheng-Wen Wu, “Test Integration of Core-Based System-on-Chip Supporting Delay Test”Laboratory for Reliable Computing (LARC) Department of Electrical Engineering National Tsing Hua University Hsinchu, Taiwan 30013, ROC, Proc. 16th VLSI/CAD P2-71. [Waayers 05]Tom Waayers , Richard Morren , Roberto Grandi , “Definition of a robust Modular SOC Test Architecture; Resurrection of the single TAM daisy-chain” , Proc. IEEE International Test Conference. (ITC), 2005. pp.610-619. [Wu 06] Po-Lin Wu ,”Implementation of an IEEE 1500 Test Wrapper Generation, Validation and Power Estimation Tool” , National Taiwan Univ. Master thesis, 2006. [Wang 06] Laung-Terng Wang , Cheng-Wen Wu ,Xiaoqing Wen , “VLSI Principles and Architectures” ,Morgan Kaufmann Publishers ,Inc 2006. [Xu 05] Qiang Xu , Nicola Nicolici , “Modular SOC Testing With Reduced Wrapper Count” , Proc. IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 24, pp. 1894-1908, Dec. 2005. [Young 94] Young . G ,McHugh . P , “Interfacing IEEE 1149.5 to IEEE 1149.1” , Proc.Electro/94 International. Conference ,Combined Volumes10-12 May 1994 pp:768 – 781. [Zorian 05]Yervant Zorian , Avetik Yessayan , “IEEE 1500 Utilization in SOC Design and Test” , Proc. IEEE International Test Conference(ITC), 2005.pp: 543- 552. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/31213 | - |
dc.description.abstract | 本論文在延遲錯誤測試方面,我們提出了兩種延遲錯誤測試方法,稱之為G1P2以及G2P2。G1P2為一省測試面積及測試時間的延遲錯誤測試方法,而G2P2為一全速(At-Speed)延遲錯誤測試方法。我們的延遲錯誤測試方法或許需增加若干之測試點,我們亦有提出測試點之選擇方法。我們也實作了配合IEEE 1500標準測試封套的自動化系統晶片(System on Chip, SoC) 驗證軟體。透過此工具自動產生之驗證用測試平臺(TestBench)可支援單一黏著性錯誤模型(Single stuck-at fault model),以及延遲錯誤模型(Delay fault model)的測試。本論文亦依IEEE 1450.6標準核心測試語言,實作了核心測試語言產生器(CTL Generator),產生所需之系統晶片測試圖樣(Test Patterns)。 | zh_TW |
dc.description.abstract | In this thesis, two delay fault test methods are proposed,G1P2 and G2P2. G1P2 is a delay fault test method which may save test area and test time. G2P2 is a precise At-Speed delay fault test method. Our delay fault test methods would need some test points. A test point selection method is presented.An automatic testbench generator for testing a SoC(System on Chip) with IEEE 1500 wrapped cores is implemented. The generated testbench is flexible for testing the SoC in either single stuck-at fault model or delay fault model test applications. A CTL generator for generating SoC test patterns is also implemented. | en |
dc.description.provenance | Made available in DSpace on 2021-06-13T02:36:12Z (GMT). No. of bitstreams: 1 ntu-96-R93943081-1.pdf: 870139 bytes, checksum: dc64318e08073e2cd51762ec4481984c (MD5) Previous issue date: 2007 | en |
dc.description.tableofcontents | 口試委員會審定書...........................I
致謝................................. ....II 中文摘要.................................III 英文摘要................................ .IV 第一章 緒論...............................1 1.1 論文背景與動機........................1 1.2 論文貢獻..............................3 1.3 論文組織..............................5 第二章 論文相關背景.......................6 2.1 IEEE 1500 標準測試封套介紹...........6 2.1.1 封套介面暫存器與封套旁通暫存器......8 2.1.2 封套指令暫存器與封套介面協定.......10 2.1.3 IEEE 1500 標準測試封套之測試模式...11 2.1.4 核心測試語言(Core Test Language,CTL) ..12 2.2 階層式系統晶片測試架構介紹...............13 2.3 延遲錯誤模型的測試方法介紹...............21 2.3.1 系統晶片的延遲錯誤模型測試方法 [Wang 05] ..22 2.3.2 系統晶片的延遲錯誤模型測試方法[Chiu 05] .. 24 第三章 延遲測試DFT架構...........................27 3.1 新系統晶片延遲錯誤測試方法介紹..............28 3.2 新IEEE 1500封套架構.........................29 3.2.1 G1P2延遲錯誤模型中封套介面單元之控制.......31 3.2.2 G2P2延遲錯誤模型中封套介面單元之控制.......37 3.2.3 指令解碼器更新部分.........................44 3.2.4 G1P2並列式延遲測試模式下之路徑.............45 3.2.5 封套介面協定訊號解碼器.....................46 3.3 新系統晶片控制架構..........................47 3.3.1 封套控制介面電路更新部分...................48 3.3.2 封套控制編碼器之實作內容...................50 3.3.3 系統指令解碼器更新部分.....................52 3.3.4 轉換控制器更新部分.........................55 3.4 測試點架構..................................56 3.5 小結....................................60 第四章 系統晶片驗證軟體實作......................61 4.1 核心測試語言(CTL)產生器.................63 4.1.1 核心測試語言產生器軟體流程實作.............63 4.1.2 核心測試語言產生器軟體結構分析.............66 4.2 系統晶片驗證軟體實作流程....................75 4.2.1 系統晶片驗證實作軟體結構分析(一) ..........76 4.2.2 系統晶片驗證實作軟體結構分析(二) ..........78 4.2.3 系統晶片驗證實作軟體結構分析(三) ..........80 4.3 測試點選擇實作流程..........................83 4.3.1 使用SAT技術解測試圖樣......................85 4.3.2 測試圖樣比對演算法.........................87 第五章 實驗結果..................................91 5.1 測試時間比較............................91 5.1.1 單一黏著錯誤測試時間比較...................92 5.1.2 G1P2及G2P2模型延遲測試時間比較.............96 5.1.3 膠合邏輯測試測試時間比較...................98 5.2 測試面積比較...............................100 5.2.1 測試點數量................................100 5.2.2 輸出入端封套介面單元面積比較..............102 5.3 數據分析...................................104 5.3.1 測試面積與測試時間數據分析................104 5.3.2 測試點數量數據分析........................105 第六章 結論.....................................106 參考文獻.........................................108 | |
dc.language.iso | zh-TW | |
dc.title | 支援全速延遲測試之IEEE 1500標準測試封套設計與驗證測試方法 | zh_TW |
dc.title | IEEE 1500 Compatible Test Wrapper Design and Validation for At-Speed Delay Testing | en |
dc.type | Thesis | |
dc.date.schoolyear | 95-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 黃俊郎,黃鐘揚 | |
dc.subject.keyword | 全速,延遲,驗證,測試,系統晶片, | zh_TW |
dc.subject.keyword | IEEE 1500,Validation,At-Speed,Delay,Testing, | en |
dc.relation.page | 112 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2007-01-19 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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