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Title: | 多媒體應用的系統單晶片平台設計-以JPEG2000解碼器為例 SoC Platform Design Optimizations for Multimedia Applications-An Example for JPEG2000 Decoders |
Authors: | Guan-Hong Chen 陳冠宏 |
Advisor: | 王勝德(Sheng -De Wang) |
Keyword: | 電子層級設計軟體,處理程序層級,執行時間,系統單晶片,快取記憶體, electronic system level design tool,Transaction-Level Modeling,execution time,System-on-chip,cache, |
Publication Year : | 2007 |
Degree: | 碩士 |
Abstract: | 本論文利用CoWare 公司的Platform Architect電子層級設計軟體,來建立處理程序層級的系統單晶片平台,並以多媒體應用jpeg2000為例,做軟硬體執行時間的改善。在我們所提出的架構中,軟體負責輸入資料及控制硬體動作,硬體負責執行解碼運算。在硬體改善方面,以改善平台溝通方式為主,方法有兩種,一是減少溝通所需路徑;二是將硬體IP改成具有bus master功能後,減少由軟體控制每一筆資料傳輸的時間。而後在軟體改善方面,使用快取記憶體及編譯器參數,並針對不同的溝通方式,對應到軟體作原始碼的改寫,而後探討在不同的平台溝通架構下的執行時間改善比率。 Platform Architect, one of the CoWare corporation’s electronic system level design tool, can be used to build and simulate various virtual System-on-chip(SoC) platforms. This thesis explores a jpeg2000 decoder on SoC platforms that are based on Transaction-Level Modeling (TLM). We improve the system execution time by using both methods of hardware and software optimizations. In the hardware part, we refine the communication architecture and make use of master ports on the SoC platform to reduce communication time. In the software part, we enable caches, compiler options and rewriting parts of the source code for the different architectures to improve the system execution time. Finally we can get the best solution from exploring the hardware and software optimizations. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/28403 |
Fulltext Rights: | 有償授權 |
Appears in Collections: | 電機工程學系 |
Files in This Item:
File | Size | Format | |
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ntu-96-1.pdf Restricted Access | 2.18 MB | Adobe PDF |
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