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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 王勝德(Sheng -De Wang) | |
dc.contributor.author | Guan-Hong Chen | en |
dc.contributor.author | 陳冠宏 | zh_TW |
dc.date.accessioned | 2021-06-13T00:07:18Z | - |
dc.date.available | 2011-07-30 | |
dc.date.copyright | 2007-07-30 | |
dc.date.issued | 2007 | |
dc.date.submitted | 2007-07-28 | |
dc.identifier.citation | [1]SystemC , http://www.systemc.org/
[2]CoWare Inc., http://www.coware.com/products/platformarchitect.php [3]GWIC, http://www.jole.fi/research/gwic/ [4]G. Larsen, technical training :Transaction level Modeling,CoWare Inc. , 2005, pp. 1-5. [5]Application Note:TLM SystemC Coding Guidelines Using the Bus Simulator, CoWare Inc. ,October 01 2003, Version 4.1. [6]CoWare Model Library:AMBA Bus Library,CoWare Inc., July 2006 ,Version V2005.2.2. [7]CoWare Model Library:ARM926EJS_AHB PSP, CoWare Inc., July 2006 ,Version V2005.2.2. [8]錢偉德, ”利用Platform Architect完成ARM-Based Platform之設計與效能分析, ” CICeNEWS , December 15 2006 ,Vol. 74, pp. 3-14. [9]V. Dalal and C. P. Ravikumar “Software Power Optimizations In An Embedded System,” in Proc. VLSI Design 14th International Conference, 2001, pp. 254. [10]Application Note: Creating Platforms with Platform Creator, CoWare Inc., May 27 2005, Version 2005.1.0 . [11]CoWare Platform Architect/CoWare Virtual Platform Product Family:Analysis Manual, CoWare Inc., July 2006, Version V2005.2.2, pp. 17-27. [12]“Application Note:Software Analysis with ConvergenSC, ” CoWare Inc., May 30 2005,Version 2005.1.0 . [13]Ogawa, S.B. Noyer, P. Chauvet, and K. Shinohara, ”A Practical Approach for Bus Architecture Optimization at Transaction Level, “in Proc. European Design Automation Conference, March 2003, Vol. 2,pp. 176-181. [14]T. Lei, Y. Yanhui, and W. Shaojun, “Optimizing SoC Platform Architecture For Multimedia Applications,” in Proc. ASICON 6th International Conference On, Oct 2005, Vol. 1, pp. 94-97. [15]S. Pasrichat, N. Dutt, and M. Ben-Romdhanet, ”Extending the Transaction Level Modeling Approach for Fast Communication Architecture Exploration, ”in Proc. Design Automation Conference 41st, 2004, pp. 113-118. [16]C. N. Liu and T. H. Tsai, “SoC Platform Based Design of MPEG-2/4 AAC Audio Decoder,” Circuits and Systems, May 2005, Vol. 3, pp. 2851-2854. [17]吳欣龍, ”Introduction to AMBA Bus System,” 工研院, http://tpe-wh3.dwins.net/download/member_file/2002/soc/2002-5-1.pdf. [18]K. V. Rompaey, D. Verkest, I. Bolsens, and H. D. Man, “CoWare – A design environment for heterogeneous hardware/software systems,” in Proc. European Design Automation Conference, 1996, pp. 252-257. [19]Application Note: Bus Analysis with ConvergenSC, CoWare Inc., May 28 2005, Version 2005 .1.0 . [20]A. Wieferink, T. Kogel, and A. Hoffmann, O. Zerres, and A. Nohl, “ Session : Open Forum on SystemC, SOC INTEGRATION OF PROGRAMMABLE CORES,” IP Based Design 2003, CoWare Inc, November 2003. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/28403 | - |
dc.description.abstract | 本論文利用CoWare 公司的Platform Architect電子層級設計軟體,來建立處理程序層級的系統單晶片平台,並以多媒體應用jpeg2000為例,做軟硬體執行時間的改善。在我們所提出的架構中,軟體負責輸入資料及控制硬體動作,硬體負責執行解碼運算。在硬體改善方面,以改善平台溝通方式為主,方法有兩種,一是減少溝通所需路徑;二是將硬體IP改成具有bus master功能後,減少由軟體控制每一筆資料傳輸的時間。而後在軟體改善方面,使用快取記憶體及編譯器參數,並針對不同的溝通方式,對應到軟體作原始碼的改寫,而後探討在不同的平台溝通架構下的執行時間改善比率。 | zh_TW |
dc.description.abstract | Platform Architect, one of the CoWare corporation’s electronic system level design tool, can be used to build and simulate various virtual System-on-chip(SoC) platforms. This thesis explores a jpeg2000 decoder on SoC platforms that are based on Transaction-Level Modeling (TLM). We improve the system execution time by using both methods of hardware and software optimizations. In the hardware part, we refine the communication architecture and make use of master ports on the SoC platform to reduce communication time. In the software part, we enable caches, compiler options and rewriting parts of the source code for the different architectures to improve the system execution time. Finally we can get the best solution from exploring the hardware and software optimizations. | en |
dc.description.provenance | Made available in DSpace on 2021-06-13T00:07:18Z (GMT). No. of bitstreams: 1 ntu-96-J93921035-1.pdf: 2237198 bytes, checksum: b50a893ca6aadd397cf7033e4c54ee67 (MD5) Previous issue date: 2007 | en |
dc.description.tableofcontents | 口試委員會審定書 i
致謝 ii 中文摘要 iii 英文摘要 iv 目錄 v 圖目錄 vii 表目錄 vii 第一章:緒論 1 1.1研究動機 1 1.2研究目標和構想 1 1.3論文章節安排 2 第二章:相關研究 3 2.1處理程序層級系統平台介紹 4 2.2CoWare之匯流排模型 5 2.3Transfer層級介紹 6 2.3.1 Transfer層級傳輸方式 7 2.3.2 Transfer與周邊的傳輸關係 8 2.3.3 Transaction、Transfer和Attributes之間的組成關係 9 第三章:方法 10 3.1實驗使用到的軟體版本及工具介紹 10 3.2實驗流程 11 3.3平台建立流程 12 3.4分析流程 14 3.4.1軟體分析流程 15 第四章:實驗過程和實驗結果 20 4.1基本架構(架構一) 20 4.1.1 架構一軟體部分 22 4.1.2 架構一硬體部分 24 4.2減少傳輸路徑(架構二) 26 4.2.1 架構二軟體修改 26 4.3硬體IP的改善(架構三) 27 4.3.1 架構三軟體部分 28 4.3.2 架構三硬體部分 30 4.4軟體最佳化 32 4.4.1 開啟快取記憶體後的改善 32 4.4.2加入編譯器參數優化級別(-O1、-O2)與優化方向(-Otime) 34 4.4.3 改寫原始碼 35 4.5實驗結果 36 第五章:結論 39 參考文獻 40 | |
dc.language.iso | zh-TW | |
dc.title | 多媒體應用的系統單晶片平台設計-以JPEG2000解碼器為例 | zh_TW |
dc.title | SoC Platform Design Optimizations for Multimedia Applications-An Example for JPEG2000 Decoders | en |
dc.type | Thesis | |
dc.date.schoolyear | 95-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 洪士灝(Shih-Hao Hung),顏嗣鈞(Hsu-chun Yen) | |
dc.subject.keyword | 電子層級設計軟體,處理程序層級,執行時間,系統單晶片,快取記憶體, | zh_TW |
dc.subject.keyword | electronic system level design tool,Transaction-Level Modeling,execution time,System-on-chip,cache, | en |
dc.relation.page | 41 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2007-07-30 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
顯示於系所單位: | 電機工程學系 |
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