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Title: | 晶片間連線之時脈偏差補償器設計與實作 Design and Implementation of a Chip-to-Chip Interconnect Clock Skew Compensator |
Authors: | Chun-Yu Chiu 邱俊毓 |
Advisor: | 陳少傑(Sao-Jie Chen) |
Co-Advisor: | 張棋(Chi Chang) |
Keyword: | 時脈偏差,補償,校正,晶片互連, DLL,skew compensation,tracking system,clock skew, |
Publication Year : | 2007 |
Degree: | 碩士 |
Abstract: | 在過去幾年,隨著CMOS製程技術的發展,以及處理器運算能力快速提升,工程師做了許多努力在提升晶片間輸入/輸出的速度,以維持高容量網路和高性能電腦系統的頻寬需要。工程師投入大量的研究與發展心力在操作在6Gb/s甚至更快的高速低功率串列收發器上。
在高速操作和高頻寬的需求下,取樣資料的時序邊界越來越小,而連結的效能差別會限制住資料能夠傳輸的速率。如何提升資料傳送或接收的質量就成為一個重要的課題。一個同時含有多重相位時脈產生器以及每一接腳一個時脈偏差補償器的時脈資料追蹤系統就是此問題的解答。 為了在接收端將輸入的資料串列從類比訊號轉為數位形式,我們採用一個架構能夠藉由非同步的訊號去對資料正確取樣。此架構會相對應輸入的資料串列去產生一個特別的時脈恰巧校準在資料中央。當輸入的資料速率為6.4-Gb/s時,此架構還原輸入的資料串列轉為兩筆3.2-Gb/s的資料串列。 As the demand of high bandwidth links for high speed communication is increasing, the timing margin in high speed communication is therefore shrinking, and a poor performance of the link will definitely limit the data rate. Thus, how to improve the quality of the transmitted and received data becomes an important and challenging design issue nowadays. A clock data tracking system is the solution of this issue which contains a global multiphase clock generator and one clock skew compensator in each pin. In order to recover the input data stream from analog signal to digital binary form, we use an architecture which samples data correctly from the mesochronous signals in this work. The architecture generates a particular clock according to the input data stream which is aligned at the middle of the data bit. With a data rate of 6.4-Gb/s, the architecture recovers the input data stream into 2 parallel data at 3.2-Gb/s. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/27564 |
Fulltext Rights: | 有償授權 |
Appears in Collections: | 電子工程學研究所 |
Files in This Item:
File | Size | Format | |
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ntu-96-1.pdf Restricted Access | 4.68 MB | Adobe PDF |
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