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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳少傑(Sao-Jie Chen) | |
dc.contributor.author | Chun-Yu Chiu | en |
dc.contributor.author | 邱俊毓 | zh_TW |
dc.date.accessioned | 2021-06-12T18:09:58Z | - |
dc.date.available | 2010-11-15 | |
dc.date.copyright | 2007-11-15 | |
dc.date.issued | 2007 | |
dc.date.submitted | 2007-10-30 | |
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[2] C. K. Lin, “Design and Implementation of CMOS Delay-Locked Loop for Interconnection Deskew,” Master Thesis, Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan, June 2006. [3] A. Tanabe, M. Umetani, I. Fujiwara, T. Ogura, K. Kataoka, M. Okihara, H. Sakuraba, T. Endoh, and F. Masuoka, “0.18-m CMOS 10-Gb/s Multiplexer/Demultiplexer ICs Using Current Mode Logic with Tolerance to Threshold Voltage Fluctuation,” IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 988-996, Jun. 2001. [4] H. Hassan, M. Anis, and M. Elmasry, “MOS Current Mode Circuits: Analysis, Design, and Variability,” IEEE Trans. on VLSI Systems, vol. 13, no. 8, pp. 885-898, Aug. 2005. [5] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, New York, 2001. [6] J.G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732, Nov. 1996. [7] P. Heydari, “Design and Analysis of Low-Voltage Current-Mode Logic Buffers,” in Proc. IEEE Int. Symp. Quality Electrical Design, pp. 293-298, Mar. 2003. [8] E. Yeung and M. A. Horowitz, “A 2.4Gb/s/pin Simulation Bidirectional Parallel Link with Per-Pin Skew Compensation,” IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1619-1628, Nov. 2000. [9] S. Sidiropoulos and M. A. Horowitz, “A Semidigital Dual Delay-Locked Loop,” IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 1683-1692, Nov. 1997. [10] A. L. Coban, M. H. Koroglu and K. A. Ahmed, “A 2.5–3.125-Gb/s Quad Transceiver with Second-Order Analog DLL-Based CDRs,” IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1940-1947, Sep. 2005. [11] J.E. Jaussi, G. Balamurugan, D.R. Johnson, B. Casper, A. Martin, J. Kennedy, N. Shanbhag and R, Mooney, “8-Gb/s Source-Synchronous I/O Link with Adaptive Receiver Equalization, Offset cancellation, and Clock De-skew,” IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 80 – 88, Jan. 2005. [12] B. Casper, A. Martin, J. E. Jaussi, J. Kennedy and R. Mooney, “An 8-Gb/s Simultaneous Bidirectional Link with On-die Waveform Capture” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2111 – 2120, Dec 2003. [13] G. Balamurugan, J. Jaussi, D. R. Johnson, B. Casper, A. Martin, J. Kennedy, R. Mooney, and N. Shanbhag, “Receiver Adaptation and System Characterization of an 8Gps Source-Synchronous I/O Link using On-die Circuits in 0.13 μm CMOS,” in VLSI Symp. Tech. Dig., Jun. 2004, pp. 356-359. [14] S. Sidiropoulos and M.A. Horowitz, “A 700-Mb/s/pin CMOS Signaling Interface Using Current Integrating Receivers,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 681-690, May 1997. [15] J. E. Jaussi, G. Balamurugan, D. R. Johnson, B. K. Casper, A. Martin, J. T. Kennedy, N. Shanbhag, and R. Mooney, “8 Gb/s Source-Synchronous I/O Link with Adaptive Receiver Equalization, Offset Cancellation and Clock De-skew,” in IEEE International Solid-State Circuits Conference Dig. Tech. Papers, Feb. 2004, pp. 244-246. [16] T. C. Lee and B. Razavi, “A 125-MHz CMOS Mixed-Signal Equalizer for Gigabit Ethernet on Copper Wire,” in Proc. IEEE Custom Integrated Circuits Conference, pp. 131-134, 2001. [17] T. Sato, Y. Nishio, T. Sugano and Y. Nakagome, “A 5-GByte/s Data-Transfer Scheme with Bit-to-Bit Skew Control for Synchronous DRAM,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 653 – 660, May 1999. [18] C. W. Chen, “A Tracking Data Recovery System for Inter-Chip Signaling,” Master Thesis, Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan, June 2000. [19] C. H. Sun, “Design of CMOS DLL and 1.25Gb/s Data Recovery,” Master Thesis, Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan, June 2002. [20] T. H. Lee and J. F. Bulzacchelli, “ A 155-MHz Clock Recovery Delay- and Phase-Locked Loop,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1736 – 1746, Dec. 1992. [21] K. Nakamura, M. Fukaishi, H. Abiko, A. Matsumoto, and M. Yotsuyanagi, “A 6Gbps CMOS Phase Detecting DEMUX Module Using Half-Frequency Clock,’ in Proc. of IEEE Symposium on VLSI Circuits, pp. 196-197, Jun 1998. [22] M. Y. He, and J. Poulton, “A CMOS Mixed-Signal Clock and Data Recovery Circuit for OIF CEI-6G+ Backplane Transceiver,” IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 597 – 606, Mar. 2006. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/27564 | - |
dc.description.abstract | 在過去幾年,隨著CMOS製程技術的發展,以及處理器運算能力快速提升,工程師做了許多努力在提升晶片間輸入/輸出的速度,以維持高容量網路和高性能電腦系統的頻寬需要。工程師投入大量的研究與發展心力在操作在6Gb/s甚至更快的高速低功率串列收發器上。
在高速操作和高頻寬的需求下,取樣資料的時序邊界越來越小,而連結的效能差別會限制住資料能夠傳輸的速率。如何提升資料傳送或接收的質量就成為一個重要的課題。一個同時含有多重相位時脈產生器以及每一接腳一個時脈偏差補償器的時脈資料追蹤系統就是此問題的解答。 為了在接收端將輸入的資料串列從類比訊號轉為數位形式,我們採用一個架構能夠藉由非同步的訊號去對資料正確取樣。此架構會相對應輸入的資料串列去產生一個特別的時脈恰巧校準在資料中央。當輸入的資料速率為6.4-Gb/s時,此架構還原輸入的資料串列轉為兩筆3.2-Gb/s的資料串列。 | zh_TW |
dc.description.abstract | As the demand of high bandwidth links for high speed communication is increasing, the timing margin in high speed communication is therefore shrinking, and a poor performance of the link will definitely limit the data rate. Thus, how to improve the quality of the transmitted and received data becomes an important and challenging design issue nowadays. A clock data tracking system is the solution of this issue which contains a global multiphase clock generator and one clock skew compensator in each pin.
In order to recover the input data stream from analog signal to digital binary form, we use an architecture which samples data correctly from the mesochronous signals in this work. The architecture generates a particular clock according to the input data stream which is aligned at the middle of the data bit. With a data rate of 6.4-Gb/s, the architecture recovers the input data stream into 2 parallel data at 3.2-Gb/s. | en |
dc.description.provenance | Made available in DSpace on 2021-06-12T18:09:58Z (GMT). No. of bitstreams: 1 ntu-96-R94943093-1.pdf: 4789171 bytes, checksum: fc2fd772a1b0b6e6ca8ef6ef98c45fba (MD5) Previous issue date: 2007 | en |
dc.description.tableofcontents | ABSTRACT i
LIST OF FIGURES v LIST OF TABLES viii CHAPTER 1 INTRODUCTION 1 1.1 Motivation 1 1.2 Typical Links 1 1.3 Thesis Organization 3 CHAPTER 2 BACKGROUND OF CLOCK SKEW COMPENSATION 5 2.1 Timing Margin 5 2.2 Conventional Bus Links 7 2.3 Point-to-Point Links 8 2.4 Source Synchronous Point-to-Point Parallel Link 9 2.5 Timing Recovery Architectures 12 2.5.1 PLL-based Timing Recovery Architecture 14 2.5.2 Phase-Picking-based Timing Recovery Architecture 15 CHAPTER 3 PHASE DIFFERENCE DETECTING TECHNIQUES 17 3.1 Phase Difference Detecting Techniques 17 3.1.1 2X Sampling 18 3.1.2 3X Oversampling 19 3.1.3 Subsampled Technique 22 3.2 Phase Difference Detecting Technique in this Work 26 3.2.1 Lock Algorithm 27 3.2.2 Lock and Sampling Algorithm 28 CHAPTER 4 CLOCK SKEW COMPENSATOR 33 4.1 System Architecture 33 4.2 Behavior Simulation 34 4.3 Circuits Design 36 4.3.1 Phase Interpolator 38 4.3.2 Lock Detector and Sampler Circuit 43 4.3.3 Lead/Lag Detector 44 4.3.4 Shift Register and Majority Voter 47 4.3.5 Phase Shifter and Register 48 4.3.6 Initial Condition 49 4.4 Data Transmission Phase 51 4.5 Simulation Results 54 CHAPTER 5 SCALED-DOWN SIMPLIFIED PER-PIN SKEW COMPENSATOR 59 5.1 Simplified Architecture 59 5.2 Simulation Results 64 5.3 Process Scale Down 67 CHAPTER 6 CONCLUSION 71 REFERENCE 73 | |
dc.language.iso | en | |
dc.title | 晶片間連線之時脈偏差補償器設計與實作 | zh_TW |
dc.title | Design and Implementation of a Chip-to-Chip Interconnect Clock Skew Compensator | en |
dc.type | Thesis | |
dc.date.schoolyear | 96-1 | |
dc.description.degree | 碩士 | |
dc.contributor.coadvisor | 張棋(Chi Chang) | |
dc.contributor.oralexamcommittee | 李泰成,林宗賢,游竹(Chu Yu) | |
dc.subject.keyword | 時脈偏差,補償,校正,晶片互連, | zh_TW |
dc.subject.keyword | DLL,skew compensation,tracking system,clock skew, | en |
dc.relation.page | 74 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2007-10-31 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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