應用於無線通訊之Doherty CMOS射頻功率放大器

Abstract

為了符合未來無線通訊設備的趨勢，低成本、高整合性、低消耗功率以及微小化的特性已經成為射頻前端電路的必備條件。随著CMOS製程的進步，許多電路已經整合在單一晶片上。然而，功率放大器由於其龐大的輸出功率，使其成為積體化設計中最具挑戰性的電路。但是，在個人無線通訊應用上，前端電路所需要的功率較小，因此使用CMOS製程設計功率放大器的可行性大為增加。 功率放大器消耗的能量佔據了整個無線通訊系統的一大部份。因此，其輸出效率的優劣對於電池壽命的長短具有主導性的地位。而且這個情況將會隨著資料傳輸速度以及數位調變傳輸規格對線性度要求的增加而越來越顯著。 Doherty功率放大器雖然在操作效率上有很好的表現，但是由於特性上的需求，電路所需要的面積大小使得此架構在積體化方面居於劣勢。本論文使用TSMC 0.18μm CMOS製程實現了兩個微小化的Doherty功率放大器。其中，疊接串聯式的架構將整個Doherty功率放大器完全實現於單一晶片上。在2.4GHz的操作頻段中，該電路之功率增益為12dB、最大輸出功率與P1dB的輸出功率分別為22dBm與21dBm。P1dB的PAE為14%、而在7dB的補償區(back-off region)，PAE仍可維持在10%以上。

To fulfill the requirement of future wireless communication trends, low-cost, high integration, low power consumption and miniaturization have become necessity for RF front-end circuits. With the progresses of CMOS technologies, many circuits have been realized on a single chip. However, power amplifiers are the most challenge circuits to be integrated, due to its large output power. But, for personal applications, because of relatively small power requirements, the CMOS technologies could be possible. Power consumption of power amplifiers occupies a large portion of the whole RF systems. Therefore, output efficiency of power amplifiers is dominant to battery life. Moreover, this situation will get more striking with the increase of data transmission speed and linearity requirement of digital modulation specifications. Although the Doherty power amplifier has good efficiency at power backed-off region, but its physical size makes it to have the disadvantage in integration. In this thesis two miniaturized Doherty amplifiers are implemented using TSMC 0.18μm CMOS technology, in which the cascode-cascade structure realizes Doherty amplifier structure on a single chip. At 2.45GHz, this circuit achieves 12dB power gain. Its maximum and P1dB output power are 22dBm and 21dBm respectively. PAE at P1dB is 14% and the PAE at power 7dB back-off from P1dB is still above 10%.