請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26959完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳怡然(Yi-Jan Emery Chen) | |
| dc.contributor.author | Li-Yuan Yang | en |
| dc.contributor.author | 楊禮源 | zh_TW |
| dc.date.accessioned | 2021-06-08T07:34:29Z | - |
| dc.date.copyright | 2008-03-25 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-02-29 | |
| dc.identifier.citation | [1] 黃培倫, “WLAN產業現況,” Fubon Securities Investment Monthly, pp. 82-87, Jul. 15 2004.
[2] 潘積桂, “On the channel estimation of modified MT-CDMA with code transmit diversity,“ 碩士論文, 國立中山大學通訊工程研究所, Jul. 2004. [3] V. Chakravarthy, A. S. Nunez, and J. P. Stephens, “TDCS, OFDM, and MC-CDMA: A brief tutorial,“ IEEE Commun. Mag., vol. 43, no. 9, pp. 11-16, Sep. 2005. [4] H. Ochiai, and H. Imai, “On the distribution of the peak-to-average power ratio in OFDM signals,” IEEE Trans. Commun., vol. 49, no. 2, pp. 282-289, Feb. 2001. [5] J. Kang, D. Yu, K. Min, and B. Kim, “A ultra-high PAE Doherty amplifier based on 0.13-μm CMOS process,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 9, pp. 505-507, Sep. 2006. [6] S. C. Cripps, RF Power Amplifiers for Wireless Communications. Norwood, MA: Artech House, 1999. [7] J. Nam, and B. Kim, “The Doherty power amplifier with on-chip dynamic bias control circuit for handset application,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 4, pp. 633-642, Apr. 2007. [8] Y. Yang, J. Cha, B. Shin, and B. Kim, “A fully matched N-way Doherty amplifier with optimized linearity,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 3, Mar. 2003. [9] K. Choi, and D. J. Allstot, “Parasitic-aware design and optimization of a CMOS RF power amplifier,“ IEEE Trans. Circuits Syst. I, vol. 53, no. 1, Jan. 2006. [10] J. Kang, A. Hajimiri, and B. Kim, “A single-chip linear CMOS power amplifier for 2.4GHz WLAN,” in IEEE Int. Solid-State Circuits Conf., pp. 761-769, Feb. 2006. [11] M. Iwamoto, A. Williams, P. Chen, A. G. Metzger, L. E. Larson, and P. M. Asbeck, “An extended Doherty amplifier with high efficiency over a wide power range,“ IEEE Trans. Microw. Theory Tech., vol. 49, no. 12, pp. 2472-2479, Dec. 2001. [12] J. Kim, J. Cha, I. Kim, and B. Kim, “Optimum operation of asymmetrical-cells-based linear Doherty power amplifiers-uneven power drive and power matching,“ IEEE Trans. Microw. Theory Tech., vol. 53, no. 5, pp. 1802-1809, May 2005. [13] B. Shin, J. Cha, Y. Y. Woo, J. Yi, and B. Kim, “Linear power amplifier based on 3-Way Doherty amplifier with predistorter,“ in IEEE MTT-S Int. Microw. Symp. Dig., vol. 3, pp. 2027-2030, Jun. 2004. [14] J. Jung, U. Kim, J. Jeon, J. Kim, K. Kang, and Y. Kwon, “A new series-type Doherty amplifier for miniaturization,“ in IEEE RFIC Symp. Dig., pp. 259-262, Jun. 2005. [15] T. Sowlati, and D. M. W. Leenaerts, “A 2.4-GHz 0.18-μm CMOS self-biased cascode power amplifier,” IEEE J. Solid-State Circuits, vol. 38, no. 8, pp. 1318-1324, Aug. 2003. [16] J. N. Burghartz, M. Hargrove, C. S. Webster, R. A. Groves, M. Keene, K. A. Jenkins, R. Logan, and E. Nowak, “RF potential of a 0.18-μm CMOS logic device technology,“ IEEE Trans. Electron Devices, vol. 47, no. 4, pp. 864-870, Apr. 2000. [17] C. Tongchoi, M. Chongcheawchamnan, and A. Worapishet, “Lumped element based Doherty power amplifier topology in CMOS process,“ in Proc. IEEE Int. Symp. Circuits Syst., vol. 1, pp.445-448, May 2003. [18] S. J. Parisi, “180˚ lumped element hybrid,“ in IEEE MTT-S Int. Microw. Symp. Dig., vol.3, pp. 1243-1246, Jun. 1989. [19] M. A. K., M. Shirasgaonkar, and R. M. Patrikar, “Power amplifier linearization using a diode,“ IEEE MELECON, 16-19, pp. 173-176, May 2006. [20] C.-C. Yen, and H.-R. Chuang, “A 0.25-μm 20-dBm 2.4-GHz CMOS power amplifier with an integrated diode linearizer,“ IEEE Microw. Wireless Compon. Lett., vol. 13, no. 2, pp. 45-47, Feb. 2003. [21] J. Cha, Y. Yang, and B. Kim, “An adaptive bias controlled power amplifier with a load-modulated combining scheme for high efficiency and linearity,“ in IEEE MTT-S Int. Microw. Symp. Dig., pp. 81-84, Jun. 2003. [22] Y.-J. E. Chen, C.-Y. Liu, T.-N. Luo, and D. Heo, “A high-efficient CMOS RF power amplifier with automatic adaptive bias control,“ IEEE Microw. Wireless Compon. Lett., vol. 16, no. 11, pp. 615-617, Nov. 2006. [23] R. Ludwig, and P. Bretchko, RF Circuit Design Theory and Applications. Prentice-Hall, Inc., 2000. [24] S. C. Cripps, Advanced Techniques in RF Power Amplifier Design. Norwood, MA: Artech House, 2002. [25] Y. Yang, J. Yi, Y. Y. Woo, and B. Kim, “Optimum design for linearity and efficiency of a microwave Doherty amplifier using a new load matching technique,“ Microwave Journal, Dec. 2001. [26] Y.-J. E. Chen, C.-Y. Liu, T.-N. Luo, and D. Heo, “A high-efficient CMOS RF power amplifier with automatic adaptive bias control,“ IEEE Microw. Wireless Compon. Lett., vol. 16, no. 11, pp. 615-617, Nov. 2006. [27] K.-O. Sun, H.-J. Kim, C.-C Yen, and D. V. D. Weide, “A scalable reflection type phase shifter with large phase variation,“ IEEE Microw. Wireless Compon. Lett., vol. 15, no. 10, Oct. 2005. [28] C.-Y. Liu, “IEEE 802.11b/g high efficiency CMOS power amplifier with an integrated adaptive bias circuit,“ M.S. thesis, Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan, Jan. 2006 [29] R. Gupta, B. M. Ballweber, and D. J. Allstot, “Design and optimization of CMOS RF power amplifiers,“ IEEE J. Solid-State Circuits, vol. 36, no. 2, Feb. 2001. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26959 | - |
| dc.description.abstract | 為了符合未來無線通訊設備的趨勢，低成本、高整合性、低消耗功率以及微小化的特性已經成為射頻前端電路的必備條件。随著CMOS製程的進步，許多電路已經整合在單一晶片上。然而，功率放大器由於其龐大的輸出功率，使其成為積體化設計中最具挑戰性的電路。但是，在個人無線通訊應用上，前端電路所需要的功率較小，因此使用CMOS製程設計功率放大器的可行性大為增加。
功率放大器消耗的能量佔據了整個無線通訊系統的一大部份。因此，其輸出效率的優劣對於電池壽命的長短具有主導性的地位。而且這個情況將會隨著資料傳輸速度以及數位調變傳輸規格對線性度要求的增加而越來越顯著。 Doherty功率放大器雖然在操作效率上有很好的表現，但是由於特性上的需求，電路所需要的面積大小使得此架構在積體化方面居於劣勢。本論文使用TSMC 0.18μm CMOS製程實現了兩個微小化的Doherty功率放大器。其中，疊接串聯式的架構將整個Doherty功率放大器完全實現於單一晶片上。在2.4GHz的操作頻段中，該電路之功率增益為12dB、最大輸出功率與P1dB的輸出功率分別為22dBm與21dBm。P1dB的PAE為14%、而在7dB的補償區(back-off region)，PAE仍可維持在10%以上。 | zh_TW |
| dc.description.abstract | To fulfill the requirement of future wireless communication trends, low-cost, high integration, low power consumption and miniaturization have become necessity for RF front-end circuits. With the progresses of CMOS technologies, many circuits have been realized on a single chip. However, power amplifiers are the most challenge circuits to be integrated, due to its large output power. But, for personal applications, because of relatively small power requirements, the CMOS technologies could be possible.
Power consumption of power amplifiers occupies a large portion of the whole RF systems. Therefore, output efficiency of power amplifiers is dominant to battery life. Moreover, this situation will get more striking with the increase of data transmission speed and linearity requirement of digital modulation specifications. Although the Doherty power amplifier has good efficiency at power backed-off region, but its physical size makes it to have the disadvantage in integration. In this thesis two miniaturized Doherty amplifiers are implemented using TSMC 0.18μm CMOS technology, in which the cascode-cascade structure realizes Doherty amplifier structure on a single chip. At 2.45GHz, this circuit achieves 12dB power gain. Its maximum and P1dB output power are 22dBm and 21dBm respectively. PAE at P1dB is 14% and the PAE at power 7dB back-off from P1dB is still above 10%. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T07:34:29Z (GMT). No. of bitstreams: 1 ntu-97-R94943090-1.pdf: 3202839 bytes, checksum: 2377e83f5cac6d7f04572cd4999a0106 (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | 口試委員會審定書………………………………………………………………………I
誌謝…………………………………………………………………………………….III 摘要……………………………………………………….……………………………IV Abstract………………………………………………………………………………….V Chapter 1 Introduction…………………………………………………………………...1 1.1 Recent Developments of Wireless Communication………………………….1 1.2 Motivation……………………………………………………………………...5 1.3 Overview of This Thesis.....................................................................................7 Chapter 2 Efficiency Enhancement Technologies.............................................................8 2.1 Introduction of Power Efficiency. ......................................................................8 2.2 Envelope Elimination and Restoration.............................................................13 2.3 Chireix’s Outphasing Amplifier........................................................................15 2.4 Doherty Power Amplifier..................................................................................22 2.4.1 The Active Load-Pulling Technique..........................................................23 2.4.2 Operation Principle....................................................................................24 2.4.3 Implementation and Efficiency Characteristics.........................................30 2.5 Summary...........................................................................................................34 Chapter 3 Design and Implementation of a Fully Integrated DPA..................................36 3.1 Introduction........................................................................................................36 3.2 Physical Size Discussion of Doherty Amplifier ................................................38 3.3 Power Density of 0.18μm CMOS Technology..................................................40 3.4 The Proposed “Cascode-Cascade” Structure.....................................................42 3.5 Power Structures and Bias Networks.................................................................47 3.5.1 Main Amplifier...........................................................................................47 3.5.2 Auxiliary Amplifier....................................................................................50 3.6 Stability Considerations.....................................................................................54 3.7 Load-Pull Impedances Investigations................................................................56 3.7.1 Main Amplifier...........................................................................................56 3.7.2 Auxiliary Amplifier....................................................................................57 3.8 Matching Topologies of the Proposed Doherty Amplifier.................................59 3.9 Simulation Results.............................................................................................65 3.10 Implementation and Measurement Results......................................................71 3.11 Discussion........................................................................................................75 Chapter 4 Design and Implementation of DPA with Coupled-Inductor Structure……..78 4.1 Introduction…………………………………………………………………..78 4.2 The Proposed DPA with Coupled-Inductor Structure………………………...81 4.3 Load Impedances Investigations and Matching Topologies………………….89 4.4 Adaptive Bias of Auxiliary Amplifier………………………………………...93 4.5 Simulation Results……………………………………………………………95 4.6 Effect of Adaptive Bias Scheme………………………………………….…102 4.7 Implementation and Measurement Results………………………………….106 4.8 Discussion…………………………………………………………………...111 Chapter 5 Summary…………………………………………………………………...116 References……………………………………………………………………………..119 | |
| dc.language.iso | en | |
| dc.title | 應用於無線通訊之Doherty CMOS射頻功率放大器 | zh_TW |
| dc.title | Doherty CMOS RF Power Amplifier for Wireless Applications | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 瞿大雄(Tah-Hsiung Chu),陳信樹(Hsin-Shu Chen) | |
| dc.subject.keyword | 功率放大器,積體化,功率補償區,輸出效率,疊接串接式, | zh_TW |
| dc.subject.keyword | power amplifier,integration,power backed-off region,output efficiency,cascode-cascade, | en |
| dc.relation.page | 123 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2008-03-03 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-97-1.pdf 未授權公開取用 | 3.13 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。