兩級式匹配線反或邏輯型態之內容定址記憶體

Abstract

低功率超大型積體電路設計是目前最重要的一個議題之一，在晶片中，隨著日漸複雜的設計以及電晶體數目的不斷增加，功率節省成為了一大挑戰，為解決功率消耗的問題，目前有許多研究提出以晶片網路(Network-on-Chip)的方式來解決 IP 之間的資料傳輸問題。在晶片網路架構中，其主要元件為：交換器(switch或路由器router)及網路介面(Network Interface, NI), 而內容定址記憶體(CAM)在路由器當中是不可或缺的一部分。在本篇論文中，我們提出兩極式匹配線反或邏輯型態之內容定址記憶體來達到低功率之目的。根據本篇論文實驗結果，使用本篇所提之方法，在匹配線(matchline)上面平均可節省之功率消耗約70％。

The design of the Low power VLSI circuit is one of the most important issues at the present time technology. In the chip, with ever increasing complexity of VLSI design and transistors, the power saving becomes the noteworthy challenge. In order to solve the problem of the power consumption, the Network-on-Chip is proposed to deal with the difficulties of inter-communication between IP cores. In the NoC, the main components are Switch (or so-called Router) and Network Interface (NI, or so-called Wrapper), and CAM (Content-Addressable Memory) is an indispensable part in the router. In this thesis, we propose a NOR-type logic Content-Addressable Memory circuit of two segment matchline scheme to Reduce power consumption, in this thesis, the proposed matching scheme can be saved about 70% on average power consumption.