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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26728完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 賴飛羆 | |
| dc.contributor.author | Tse-Chun Ou Yang | en |
| dc.contributor.author | 歐陽策群 | zh_TW |
| dc.date.accessioned | 2021-06-08T07:22:50Z | - |
| dc.date.copyright | 2008-07-26 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-07-23 | |
| dc.identifier.citation | [1] T.-B. Pei and C. Zukowski, “Putting routing tables in silicon,” IEEE Network Mag., vol. 6, pp. 42–50, Jan. 1992.
[2] L. Chisvin and R. J. Duckworth, “Content-addressable and associative memory: Alternatives to the ubiquitous RAM,” IEEE Computer, vol. 22, pp. 51–64, July 1989. [3] T.-B. Pei and C. Zukowski, “VLSI implementation of routing tables: tries and CAMs,” in Proc. IEEE INFOCOM, vol. 2, 1991, pp. 515–524. [4] “Putting routing tables in silicon,” IEEE Network Mag., vol. 6, no.1, pp. 42–50, Jan. 1992. [5] A. J. McAuley and P. Francis, “Fast routing table lookup using Cams,” in Proc. IEEE INFOCOM, vol. 3, 1993, pp. 1282–1391. [6] N.-F. Huang, W.-E. Chen, J.-Y. Luo and J.-M. Chen, “Design of multi-field IPv6 packet classifiers using ternary CAMs,” in Proc. IEEE GLOBECOM, vol. 3, 2001, pp. 1877–1881. [7] G. Qin, S. Ata, I. Oka, and C. Fujiwara, “Effective bit selection methods for improving performance of packet classifications on IP routers,” in Proc. IEEE GLOBECOM, vol. 2, 2002, pp. 2350–2354. [8] H. J. Chao, “Next generation routers,” Proc. IEEE, vol. 90, no. 9, pp.1518–1558, Sep. 2002. [9] Yen-Jen Chang, Yuan-Hong Liao, and Shanq-Jang Ruan, “Improve CAM Power Efficiency Using Decoupled Match Line Scheme,” Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07 [10] Kostas Pagiamtzis, and Ali Sheikholeslami, “Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 3, MARCH 2006 [11] H. Kadota et al., “An 8-kbit content-addressable and reentrant memory,” IEEE J. Solid-State Circuits, vol. SC-20, no. 5, pp. 951–957,Oct. 1985. [12] T. Chandler I. Arsovski and A. Sheikholeslami. “A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme.” IEEE J. Solid-State Circuits, 38(1):155 – 158, January 2003. [13] I. Arsovski and A. Sheikholeslami. “A current-saving match-line sensing scheme for content-addressable memories.” In IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pages 304 – 305, 2003. [14] Behzad Razavi “Design of Analog CMOS integrated Circuits” University of California, Los Angeles. [15] C.A. Zukowski and S.-Y. Wang.'Use of selective precharge for lowpower content-addressable memories.' In Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), volume 3,pages 1788 – 1791, 1997. [16] K. Pagiamtzis and A. Sheikholeslami. ”Pipelined match-lines and hierarchical searchlines for low-power content-addressable memories.” In Proc. IEEE Custom Integrated Circuits Conf. (CICC), pages 383 – 386, 2003. [17] K. Pagiamtzis and A. Sheikholeslami, “A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1512–1519, September 2004. [18] G. Kasai, Y. Takarabe, K. Furumi, and M. Yoneda, “200 MHz/200 MSPS 3.2 W at 1.5 V Vdd, 9.4 Mbits ternary CAM with new charge injection match detect circuits and bank selection scheme,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2003, pp. 387–390. [19] Kuo-Hsing Cheng; Chia-Hung Wei; Shu-Yu Jiang;” Static divided word matching line for low-power Content Addressable Memory design.” Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on Volume 2, 23-26 May 2004 Page(s):II - 629-32 Vol.2 [20] Bart Van Zeghbroeck “ Principles of Semiconductor Devices ”, http://ece-www.colorado.edu/~bart/book/book/append/quickhtm,2006-bart@colorado.edu [21] Y.-J. Chang “Two-layer hierarchical matching method for energy-efficient CAM design” ELECTRONICS LETTERS 18th January 2007 Vol.43 No.2 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26728 | - |
| dc.description.abstract | 低功率超大型積體電路設計是目前最重要的一個議題之一，在晶片中，隨著日漸複雜的設計以及電晶體數目的不斷增加，功率節省成為了一大挑戰，為解決功率消耗的問題，目前有許多研究提出以晶片網路(Network-on-Chip)的方式來解決 IP 之間的資料傳輸問題。在晶片網路架構中，其主要元件為：交換器(switch或路由器router)及網路介面(Network Interface, NI), 而內容定址記憶體(CAM)在路由器當中是不可或缺的一部分。在本篇論文中，我們提出兩極式匹配線反或邏輯型態之內容定址記憶體來達到低功率之目的。根據本篇論文實驗結果，使用本篇所提之方法，在匹配線(matchline)上面平均可節省之功率消耗約70％。 | zh_TW |
| dc.description.abstract | The design of the Low power VLSI circuit is one of the most important issues at the present time technology. In the chip, with ever increasing complexity of VLSI design and transistors, the power saving becomes the noteworthy challenge. In order to solve the problem of the power consumption, the Network-on-Chip is proposed to deal with the difficulties of inter-communication between IP cores. In the NoC, the main components are Switch (or so-called Router) and Network Interface (NI, or so-called Wrapper), and CAM (Content-Addressable Memory) is an indispensable part in the router. In this thesis, we propose a NOR-type logic Content-Addressable Memory circuit of two segment matchline scheme to Reduce power consumption, in this thesis, the proposed matching scheme can be saved about 70% on average power consumption. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T07:22:50Z (GMT). No. of bitstreams: 1 ntu-97-J95921007-1.pdf: 881080 bytes, checksum: 68d81619f243639eb0adaaffa4ff049a (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | Chapter 1. Introduction 1
1.1. Development 1 1.2. About the CMOS 3 1.3. MOS Device Capacitances 4 1.4. MOSFET Circuits and Technology 6 1.5. Power Consumption of CMOS Circuit 8 1.5.1. Static Power Consumption 8 1.5.2. Dynamic Power Consumption 12 Chapter 2. Background 13 2.1. Application of CAM 13 2.2. Content Addressable Memory (CAM) Cell 15 2.2.1. XNOR- Cell 15 2.2.2. XOR-Cell 16 2.3. Matchline Sensing 18 2.3.1. Power Consumption 18 2.3.2. Matchline Delay 19 2.3.3. Charge Sharing 20 2.4. The Basic Structure of CAM 21 2.4.1. NOR type v 22 2.4.2. NAND type 24 Chapter 3. Reducing Power Consumption 26 3.1. The Method of Matchline 26 3.1.1. Current-Race Scheme 26 3.1.2. Selective-Precharge Scheme 27 3.1.3. Pipelining Scheme 28 3.1.4. Low-Swing Schemes 30 3.2. The Method of Searchline 32 Chapter 4. Proposed CAM 34 4.1. Matchline Scheme of two Sections Type Structure 34 4.1.1. Static Divided Word Matchline 35 4.1.2. Decoupled Matchline Scheme 37 4.1.3. Two-layer hierarchical matching method 39 4.2. The Proposed Matchline Scheme 41 4.2.1. Proposed Architecture 41 4.2.2. Implementation Topic 45 Chapter 5. Simulation Results 48 5.1. Performance 48 5.2. Power and Energy 49 Chapter 6. Conclusions 52 Bibliography 53 | |
| dc.language.iso | en | |
| dc.subject | 匹配線 | zh_TW |
| dc.subject | 內容定址記憶體 | zh_TW |
| dc.subject | 路由器 | zh_TW |
| dc.subject | 低功率 | zh_TW |
| dc.subject | 晶片網路 | zh_TW |
| dc.subject | Router | en |
| dc.subject | Low-power | en |
| dc.subject | Network-on-Chip | en |
| dc.subject | CAM | en |
| dc.subject | matchline | en |
| dc.title | 兩級式匹配線反或邏輯型態之內容定址記憶體 | zh_TW |
| dc.title | NOR-type logic Content-Addressable Memory circuit of two segment matchline schem | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 張孟洲,張延任,李鴻璋,蔡坤霖 | |
| dc.subject.keyword | 內容定址記憶體,匹配線,路由器,低功率,晶片網路, | zh_TW |
| dc.subject.keyword | CAM,matchline,Router,Low-power,Network-on-Chip, | en |
| dc.relation.page | 54 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2008-07-23 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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