動態部份可重組技術於FPGA系統功耗降低之應用

Abstract

近年來，具備可重複規劃特性的FPGA已逐漸地整合至許多應用當中，透過重複規劃FPGA的內部電路結構，使得產品的壽命得以延長，在功能上也俱備更佳的彈性，只是和ASIC相較之下，其較高的功率消耗一直是為人詬病的問題。在本論文中，我們提出使用FPGA動態部份重組的機制來降低當SOPC系統閒置時的消耗功率。在傳統的SOPC系統應用裡，當系統不需要處理資料時，其系統中的週邊裝置通常還是處在工作或是被規劃的狀態，如此一來對於系統的功率消耗而言，都是無謂浪費。我們成功的實作出動態部份重組的SOPC架構，使FPGA在工作的狀態下可以迅速的重新規劃內部的週邊裝置，藉由重新規劃系統架構，不僅可以使系統應用更靈活，也可以減少系統功率消耗。實驗當中也透過實際的量測，以瞭解FPGA的消耗功率。由本實驗的結果可發現，依據不同的實驗範例，可以分別使消耗功率降低15%和20%。

In recent years, FPGA has been gradually integrated into many applications through its re-programmability property to implement the required circuit, making the product life and functionality can be extended. However, as compared with ASIC de-vices, the high power consumption of FPGA has long been a criticized issue. In this thesis, we propose using the dynamic partial reconfiguration mechanism of FPGA to reduce the system power consumption when the SOPC implemented in FPGA is idle. In traditional SOPC applications, when the system does not process data, the devices with configured circuits usually are still actively working, so the system's power con-sumption is unnecessarily wasted. We successfully develop a framework and archi-tecture of SOPC to make the internal areas of circuits of FPGA can be reconfigured quickly. Through the dynamic partial reconfiguration, the proposed approach not only makes the system more flexible but also reduces the system power consumption. In the experiments, we also take the actual measurement to understand the FPGA power consumption. In our experiment, there are 15.02% and 20.4% improvement on power saving for different applications.