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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 王勝德(Sheng-De Wang) | |
| dc.contributor.author | Wen-Hui Shih | en |
| dc.contributor.author | 施文暉 | zh_TW |
| dc.date.accessioned | 2021-06-08T07:09:29Z | - |
| dc.date.copyright | 2008-08-04 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-08-01 | |
| dc.identifier.citation | [1] J. Noguera and I. O. Kennedy, 'Power Reduction in Network Equipment Through Adaptive Partial Reconfiguration,' in Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on, 2007, pp. 240-245.
[2] T. Pionteck, C. Albrecht, and R. Koch, 'A dynamically reconfigurable packet-switched network-on-chip,' in Design, Automation and Test in Europe, 2006. DATE '06. Proceedings, 2006, p. 8 pp. [3] A. Tumeo, M. Monchiero, G. Palermo, F. A. F. F. Ferrandi, and D. A. S. D. Sciuto, 'An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsb,' in VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on, 2007, pp. 449-450. [4] V. Betz, J. Rose and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs , Kluwer Academic Publishers, 1999. [5] Xilinx, Inc. 'Platform Specification Format Reference Manual,' version 5.0, 2007. [6] R. Fischer, K. Buchenrieder, and U. Nageldinger, 'Reducing the power consumption of FPGAs through retiming,' in Engineering of Computer-Based Systems, 2005. ECBS '05. 12th IEEE International Conference and Workshops on the, 2005, pp. 89-94. [7] J. H. Anderson and F. N. Najm, 'Power estimation techniques for FPGAs,' Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 12, pp. 1015-1027, 2004. [8] J.B. Kuo and S.-C. Lin, Low-Voltage SOI CMOS VLSI Devices and Circuits, John Wiley & Sons Inc, Sept. 2001. [9] T. Tuan and B. Lai, 'Leakage power analysis of a 90nm FPGA,' in Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003, 2003, pp. 57-60. [10] S. Li, S. K. Alireza, and B. Kusuma, 'Dynamic Power Consumption in Virtex™-II FPGA Family,' in Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays Monterey, California, USA: ACM, 2002. [11] M. Pedram, 'Power optimization and management in embedded systems,' in Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific, 2001, pp. 239-244. [12] Y.-H. Lu and G. De Micheli, 'Comparing system level power management policies,' Design & Test of Computers, IEEE, vol. 18, pp. 10-19, 2001. [13] C. Xiaotao, Z. Mingming, Z. Ge, A. Z. Z. Zhimin Zhang, and A. J. W. Jim Wang, 'Adaptive Clock Gating Technique for Low Power IP Core in SoC Design,' in Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on, 2007, pp. 2120-2123. [14] K. Hyung-Ock and S. Youngsoo, 'Analysis and optimization of gate leakage current of power gating circuits,' in Design Automation, 2006. Asia and South Pacific Conference on, 2006, p. 5 pp. [15] Y. Lin, L. Fei, and H. Lei, 'Circuits and architectures for field programmable gate array with configurable supply voltage,' Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 13, pp. 1035-1047, 2005. [16] Xilinx, Inc., 'Two Flows for Partial Reconfiguration: Module Based or Difference Based,' version 1.2, 2007. [17] Xilinx, Inc., XAPP139, 'Configuration and Readback of Virtex FPGAs Using JTAG Boundary-Scan,' version 1.7, 2007. [18] Xilinx, Inc., XAPP502, 'Using a Microprocessor to Configure Xilinx FPGAs via Slave Serial or SelectMAP Mode,' version 1.5, 2007. [19] 林灶生、劉紹漢, SOC系統晶片設計, 台灣: 全華, 2006. [20] Xilinx, Inc., UG081, 'MicroBlaze Processor Reference Guide,' version 7.0, 2006. [21] Xilinx, Inc., DS080, 'System ACE CompactFlash Solution,' version 1.5, 2002. [22] Xilinx, Inc., DS280, 'OPB HWICAP,' v1.00.b, 2006. [23] Xilinx, Inc., XAPP529, 'Connecting Customized IP to the MicroBlaze Soft Processor Using the Fast Simplex Link (FSL) Channel,' version 1.3, 2004. [24] Xilinx, Inc., DS449, 'Fast Simplex Link (FSL) Bus,' version 2.11a, 2007. [25] P. Sedcole, B. Blodget, T. Becker, J. A. A. J. Anderson, and P. A. L. P. Lysaght, 'Modular dynamic reconfiguration in Virtex FPGAs,' Computers and Digital Techniques, IEE Proceedings -, vol. 153, pp. 157-164, 2006. [26] H. Michael, B. Tobias, and B. Juergen, 'Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration,' in Proceedings of the 17th symposium on Integrated circuits and system design Pernambuco, Brazil: ACM, 2004. [27] Xilinx, Inc., UG210, 'ML405 Evaluation Platform User Guide,' version 1.3, 2007. [28] Xilinx, Inc., 'Virtex-4 Family Overview,' version 3.0, 2007. [29] T. S. Hall and J. O. Hamblen, 'System-on-a-programmable-chip development platforms in the classroom,' Education, IEEE Transactions on, vol. 47, pp. 502-507, 2004. [30] Xilinx, Inc., 'PlanAhead User Guide,' 2007. [31] Xilinx, Inc., 'Xilinx ML405 Schematics,' 2006. [32] Xilinx, Inc, 'Xilinx Device Drivers Documentation,' 2004. [33] Z. Mohd-Yusof, I. Suleiman, and Z. Aspar, 'Implementation of two dimensional forward DCT and inverse DCT using FPGA,' in TENCON 2000. Proceedings, 2000, pp. 242-245 vol.3. [34] H. El-Banna, A. A. El-Fattah, and W. Fakhr, 'An efficient implementation of the 1D DCT using FPGA technology,' in Engineering of Computer-Based Systems, 2004. Proceedings. 11th IEEE International Conference and Workshop on the, 2004, pp. 356-360. [35] Xilinx, Inc., XAPP610, 'Video Compression Using DCT,' version 1.3.1, 2007. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26416 | - |
| dc.description.abstract | 近年來，具備可重複規劃特性的FPGA已逐漸地整合至許多應用當中，透過重複規劃FPGA的內部電路結構，使得產品的壽命得以延長，在功能上也俱備更佳的彈性，只是和ASIC相較之下，其較高的功率消耗一直是為人詬病的問題。在本論文中，我們提出使用FPGA動態部份重組的機制來降低當SOPC系統閒置時的消耗功率。在傳統的SOPC系統應用裡，當系統不需要處理資料時，其系統中的週邊裝置通常還是處在工作或是被規劃的狀態，如此一來對於系統的功率消耗而言，都是無謂浪費。我們成功的實作出動態部份重組的SOPC架構，使FPGA在工作的狀態下可以迅速的重新規劃內部的週邊裝置，藉由重新規劃系統架構，不僅可以使系統應用更靈活，也可以減少系統功率消耗。實驗當中也透過實際的量測，以瞭解FPGA的消耗功率。由本實驗的結果可發現，依據不同的實驗範例，可以分別使消耗功率降低15%和20%。 | zh_TW |
| dc.description.abstract | In recent years, FPGA has been gradually integrated into many applications through its re-programmability property to implement the required circuit, making the product life and functionality can be extended. However, as compared with ASIC de-vices, the high power consumption of FPGA has long been a criticized issue. In this thesis, we propose using the dynamic partial reconfiguration mechanism of FPGA to reduce the system power consumption when the SOPC implemented in FPGA is idle. In traditional SOPC applications, when the system does not process data, the devices with configured circuits usually are still actively working, so the system's power con-sumption is unnecessarily wasted. We successfully develop a framework and archi-tecture of SOPC to make the internal areas of circuits of FPGA can be reconfigured quickly. Through the dynamic partial reconfiguration, the proposed approach not only makes the system more flexible but also reduces the system power consumption. In the experiments, we also take the actual measurement to understand the FPGA power consumption. In our experiment, there are 15.02% and 20.4% improvement on power saving for different applications. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T07:09:29Z (GMT). No. of bitstreams: 1 ntu-97-P95921006-1.pdf: 5009875 bytes, checksum: 718310370a860e6bcf237574616e15bf (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | 論文審定書……………………………………………………………………………i
誌謝……………………………………………………………………………………ii 中文摘要………………………………………………………….…………………..iii 英文摘要………………………………….……………………….………………….iv 目錄……………………………………………………………..……………………..v 圖目錄…………………………………………………………………………..……vii 表目錄………………………………………………………….……………………..ix 第一章 緒論………………………………….…………………..………………….1 1.1 研究動機..……………………………………………..…………………..1 1.2 研究目標....………………………………………………………………..2 1.3 章節概述..………………………………………….……………………...2 第二章 相關研究與技術.………………………………….………………………..3 2.1 FPGA概述..………………………………………………………………...3 2.2 FPGA功率消耗..…………………………………………..………………..4 2.2.1 靜態功耗..…………………………………………...…………….4 2.2.2 動態功耗..……………………………………………….………...4 2.3 降低功耗相關技術..…………………………………………….………...6 2.4 Dynamic Partial Reconfiguration概述...…………………..………..9 2.4.1 Module Based Partial Reconfiguration.……………………..9 2.4.2 Difference Based Partial Reconfiguration………………..12 2.5 FPGA規劃介面…………………………………………………………....12 2.5.1 JTAG介面………………………………………………………....12 2.5.2 SelectMAP介面…………………………………………………..13 第三章 可重組系統架構…………………………………………………………..15 3.1 SOC及SOPC 概述………………………………………………………..15 3.2 Dynamic Partial Reconfiguration Architecture………………....16 3.3.1 MicroBlaze……………………………………………………....17 3.3.2 System ACE……………………………………………………....17 3.3.3 HWICAP…………………………………………………………....19 3.3.4 FSL………………………………………………………………..20 3.3.5 Bus Macros……………………………………………………….24 3.3 Xilinx ML-405實驗平台…………………………………………….......26 第四章 設計流程…………………………………………………………………..28 4.1 系統設計流程…………………………………………………………....28 4.2 EDK（Xilinx Embedded Development Kit）………………………....29 4.3 ISE（Xilinx Integrated Software Environment）………………..30 4.4 PlanAhead………………………………………………………………..31 第五章 應用實例及實驗結果……………………………………………………..36 5.1 動態功耗量測…...…………………………………………………….....36 5.2 ICAP API………………………………………………………………....38 5.3 應用實例：2D-DCT……………………………………………………....39 5.3.1 實驗結果………………………………………..………………..42 5.4 應用實例：質數計算器………………………………………………....47 5.4.1 實驗結果………………………………………..………………..48 5.5 電源管理………………………………………………………………....51 第六章 結論與未來工作…………………………………………………………..56 6.1 結論………………………………………………………………………56 6.2 未來工作…………………………………………………………………56 參考文獻……………………………………………………………………………..58 附錄一 Xilinx EDK Embedded System Design………………………………....61 附錄二 ISE整合Bus Macro於嵌入式系統……………………………………...81 附錄三 系統程式碼………………………………………………………………..96 | |
| dc.language.iso | zh-TW | |
| dc.subject | 功耗量測 | zh_TW |
| dc.subject | FPGA | zh_TW |
| dc.subject | 功率消耗 | zh_TW |
| dc.subject | 動態部份規劃 | zh_TW |
| dc.subject | SOPC | zh_TW |
| dc.subject | Power consumption | en |
| dc.subject | Dynamic partial reconfiguration | en |
| dc.subject | Power measurement | en |
| dc.subject | SOPC | en |
| dc.subject | FPGA | en |
| dc.title | 動態部份可重組技術於FPGA系統功耗降低之應用 | zh_TW |
| dc.title | FPGA Power Saving Using Dynamic Partial Reconfiguration Techniques | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 黃俊郎(Jiun-Lang Huang),黃鐘揚(Chung-Yang Huang),鄭振牟(Chen-Mou Cheng) | |
| dc.subject.keyword | 動態部份規劃,功率消耗,功耗量測,SOPC,FPGA, | zh_TW |
| dc.subject.keyword | Dynamic partial reconfiguration,Power consumption,Power measurement,SOPC,FPGA, | en |
| dc.relation.page | 102 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2008-08-01 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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|---|---|---|---|
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