以開迴路放大器建構之高速管線式類比數位轉換器設計

Abstract

類比數位轉換器是連接真實世界與離散運算領域的關鍵元件。高速且低解析度的類比數位轉換器被廣泛地應用在高效能串列傳輸系統的前端部分。在本論文中提出以開迴路放大器取代管線式類比數位轉換器中的閉迴路放大器以突破管線式架構的速度限制。所設計的六位元800MS/s管線式類比數位轉換器其SNDR及SFDR的效能可分別達到33.7dB及47.5dB。在放大增益級採用電壓模式的開迴路放大器、使用全面增益控制電路、以及應用兩條路徑相互交錯的架構，使得所設計的管線式類比數位轉換器大幅地降低了在速度及功率上取捨的嚴苛要求。此管線式類比數位轉換器採用0.18微米CMOS製程製作，在電源電壓為1.8伏特的情況下所消耗的功率為105毫瓦，而電路所佔的有效面積僅為0.5平方毫米。最後應用所發展的具數位背景校正之線性近似技術以增進使用開迴路放大器建構的管線式類比數位轉換器之解析度。

Analog-to-Digital Converters (ADCs) are the key components which connect the real world with the discrete-computation fields. High-speed and low-resolution ADCs are wildly applied at the front end of high-performance serial-link systems. In this dissertation, replacing open-loop amplifiers with closed-loop amplifiers in the pipelined ADC are proposed to break through the speed limitation of pipelined architecture. The designed 6-b 800-MS/s pipelined A/D converter achieves SNDR and SFDR of 33.7dB and 47.5dB, respectively. Employing voltage-mode open-loop amplifiers in gain stages, global-gain control techniques, and two-bank-interleaved architecture, the proposed pipelined A/D converter relaxes stringent design trade-offs between speed and power. Fabricated in a 0.18-um CMOS technology, the ADC consumes 105mW from a 1.8-V power supply while the active area is only 0.5mm2. The linear approximation technique of the digital background calibration is proposed to enhance the resolution of the pipelined ADC with open-loop amplifiers in the end.