Please use this identifier to cite or link to this item:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/24175
Title: | 快閃記憶體轉譯層之可適性範圍的位置轉譯設計 Adaptive Range-Based Address Mapping for the Flash Translation Layer |
Authors: | Shou-Chieh Hsu 許碩傑 |
Advisor: | 郭大維(Tei-Wei Kuo) |
Keyword: | 快閃記憶體,快閃記憶體轉譯層,可適性範圍, Flash,FTL,Range-based, |
Publication Year : | 2011 |
Degree: | 碩士 |
Abstract: | 快閃記憶體的容量近年來快速的增大,而快閃記憶體轉譯層的大小
卻跟快閃記憶體的容量成正比,因此隨著快閃記憶體的容量增大,快 閃記憶體轉譯層的大小變得越來越不能接受。這個研究主要提出了一 個可適性範圍的方法,使用多種粒度的方式,可以有效率的管理快閃 記憶體轉譯層的資訊。使用多個連續的位置使用一筆目錄的方式來管 理,如此達到省空間的效果。利用這個可適性範圍的位置轉譯,快閃 記憶體轉譯資訊可以有更高的管理彈性。 In recent years, the size of the flash memory grows up rapidly. However, the size of mapping information of traditional FTL designs is direct proportion to the size of flash memory. Therefore, with the size of flash memory grows, the size of mapping information has become intolerable. In this paper, a range-based mapping mechanism is proposed to effectively maintain the mapping information, which uses multi-grained mapping mechanism to manage logical block address. To reduce RAM consumption, manage mapping information with continuous mapping in one entry. By the range-based mapping mechanism, the mapping information is managed with higher flexibility. iv |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/24175 |
Fulltext Rights: | 未授權 |
Appears in Collections: | 資訊工程學系 |
Files in This Item:
File | Size | Format | |
---|---|---|---|
ntu-100-1.pdf Restricted Access | 1.3 MB | Adobe PDF |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.