請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/24175
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 郭大維(Tei-Wei Kuo) | |
dc.contributor.author | Shou-Chieh Hsu | en |
dc.contributor.author | 許碩傑 | zh_TW |
dc.date.accessioned | 2021-06-08T05:17:41Z | - |
dc.date.copyright | 2011-08-22 | |
dc.date.issued | 2011 | |
dc.date.submitted | 2011-08-21 | |
dc.identifier.citation | [1] Flash-memory translation layer for nand flash (nftl). M-Systems, 1998.
[2] Understanding the flash translation layer (ftl) specification, http://developer.intel.com/. Technical report, Intel Corporation, Dec 1998. [3] N. Agrawal, V. Prabhakaran, T.Wobber, J. D. Davis, M. Manasse, and R. Panigrahy. Design tradeoffs for ssd performance. In USENIX 2008 Annual Technical Conference on Annual Technical Conference, pages 57–70, Berkeley, CA, USA, 2008. USENIX Association. [4] L.-P. Chang and T.-W. Kuo. An adaptive striping architecture for flash memory storage systems of embedded systems. In the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pages 187–196, 2002. [5] Y.-H. Chang, J.-W. Hsieh, and T.-W. Kuo. Endurance enhancement of flash-memory storage systems: an efficient static wear leveling design. In Proceedings of the 44th annual Design Automation Conference, DAC ’07, pages 212–217, New York, NY, USA, 2007. ACM. [6] Y.-H. Chang and T.-W. Kuo. A commitment-based management strategy for the performance and reliability enhancement of flash-memory storage systems. In ACM/IEEE Design Automation Conference (DAC), pages 858–863, July 2009. 28 [7] E. Deal. Trends in nand flash memory error correction. Technical report, Cyclic Design, June 2009. [8] A. Gupta, Y. Kim, and B. Urgaonkar. Dftl: a flash translation layer employing demand-based selective caching of page-level address mappings. SIGPLAN Not., 44:229–240, March 2009. [9] Y. I. E. Hyunjin Cho, Dongkun Shin. Kast: K-associative sector translation for nand flash memory in real-time systems. In the ACM/IEEE Design, Automation and Test in Europe (DATE), pages 507–512, April 2009. [10] J.-U. Kang, H. Jo, J.-S. Kim, and J. Lee. A superblock-based flash translation layer for nand flash memory. In Proceedings of the 6th ACM & IEEE International conference on Embedded software, EMSOFT ’06, pages 161–170, New York, NY, USA, 2006. ACM. [11] J. Kim, J. M. Kim, S. H. Noh, S. L. Min, and Y. Cho. A space-efficient flash translation layer for compactflash systems. IEEE Transactions on Consumer Electronics, Nov 2002. [12] S. Lee, D. Shin, Y.-J. Kim, and J. Kim. Last: locality-aware sector translation for nand flash memory-based storage systems. SIGOPS Oper. Syst. Rev., 42:36–42, October 2008. [13] S.-W. Lee, D.-J. Park, T.-S. Chung, D.-H. Lee, S. Park, and H.-J. Song. A log bufferbased flash translation layer using fully-associative sector translation. ACM Trans. Embed. Comput. Syst., 6, July 2007. 29 [14] Micron Technology, Inc. FNNB63A 128Gbit NAND Flash Memory Data Sheet, 2011. [15] Micron Technology, Inc. FNNB74A 64Gbit NAND Flash Memory Data Sheet, 2011. [16] C. Park, W. Cheon, J. Kang, K. Roh, W. Cho, and J.-S. Kim. A reconfigurable ftl (flash translation layer) architecture for nand flash-based applications. ACM Trans. Embed. Comput. Syst., 7:38:1–38:23, August 2008. [17] D. Park, B. Debnath, and D. Du. Cftl: a convertible flash translation layer adaptive to data access patterns. In Proceedings of the ACM SIGMETRICS international conference on Measurement and modeling of computer systems, SIGMETRICS ’10, pages 365–366, New York, NY, USA, 2010. ACM. [18] Samsung Electronics. K9F8G08UXM 1G x 8 Bit NAND Flash Memory Data Sheet, March 2007. [19] SpecTek Technology, Inc. MT29F256G08CUCBB 256Gbit NAND Flash Memory Data Sheet, September 2008. [20] C.-H. Wu and T.-W. Kuo. An adaptive two-level mnagement for the flash translation layer in embedded systems. In the IEEE/ACM Iinternational Conference on Computer-Aided Design (ICCAD), pages 601–606, 2006. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/24175 | - |
dc.description.abstract | 快閃記憶體的容量近年來快速的增大,而快閃記憶體轉譯層的大小
卻跟快閃記憶體的容量成正比,因此隨著快閃記憶體的容量增大,快 閃記憶體轉譯層的大小變得越來越不能接受。這個研究主要提出了一 個可適性範圍的方法,使用多種粒度的方式,可以有效率的管理快閃 記憶體轉譯層的資訊。使用多個連續的位置使用一筆目錄的方式來管 理,如此達到省空間的效果。利用這個可適性範圍的位置轉譯,快閃 記憶體轉譯資訊可以有更高的管理彈性。 | zh_TW |
dc.description.abstract | In recent years, the size of the flash memory grows up rapidly. However,
the size of mapping information of traditional FTL designs is direct proportion to the size of flash memory. Therefore, with the size of flash memory grows, the size of mapping information has become intolerable. In this paper, a range-based mapping mechanism is proposed to effectively maintain the mapping information, which uses multi-grained mapping mechanism to manage logical block address. To reduce RAM consumption, manage mapping information with continuous mapping in one entry. By the range-based mapping mechanism, the mapping information is managed with higher flexibility. iv | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T05:17:41Z (GMT). No. of bitstreams: 1 ntu-100-R98922055-1.pdf: 1329637 bytes, checksum: 9274692850ae8d7731f3c779202b8021 (MD5) Previous issue date: 2011 | en |
dc.description.tableofcontents | Acknowledgments i
中文摘要ii Abstract iii 1 Introduction 1 2 System Architecture and Motivation 4 3 An Adaptive Range Mapping Mechanism for Flash Translation Layer 9 3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 An Adaptive Mapping Mechanism . . . . . . . . . . . . . . . . . . . . . 11 3.2.1 A Binary Search Tree with Two Kinds of Node . . . . . . . . . . 11 3.2.2 Rotational Operation . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 Tree Adaptation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.1 Split/Merge Operation . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.2 Eviction Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.1 Allocation Policy . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 Performance Evaluation 22 4.1 Performance Metrics and Experiment Setup . . . . . . . . . . . . . . . . 22 4.2 Experiment Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2.1 RAM consumption . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2.2 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 CONCLUSION 26 Bibliography 28 | |
dc.language.iso | en | |
dc.title | 快閃記憶體轉譯層之可適性範圍的位置轉譯設計 | zh_TW |
dc.title | Adaptive Range-Based Address Mapping for the Flash Translation
Layer | en |
dc.type | Thesis | |
dc.date.schoolyear | 99-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 逄愛君(Ai-Chun Pang),陳銘憲(Ming-Syan Chen),黃佑充(YC.Huang),張原豪(Yuan-Hao Chang),薛智文(Steven C.-W. Hsueh) | |
dc.subject.keyword | 快閃記憶體,快閃記憶體轉譯層,可適性範圍, | zh_TW |
dc.subject.keyword | Flash,FTL,Range-based, | en |
dc.relation.page | 30 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2011-08-21 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
顯示於系所單位: | 資訊工程學系 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-100-1.pdf 目前未授權公開取用 | 1.3 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。