三維微型熱電致冷元件之研製

Abstract

本論文以透過將微型熱電致冷元件三維化，預計以三維立體微米結構，增加單位面積的P-N Couple數，減少熱傳導率，進而有效提升熱電元件的整體效率。 整體熱電元件的製程規劃包含21項半導體製程，其中使用多達5到光罩設計，所有步驟均相容於現今半導體製程，此結構設計可以大幅幫助所製作出來的熱電元件的實用性以及與其他電子元件的相容性。本論文實驗中使用電漿輔助化學氣相沉積（Plasma Enhanced Chemical Vapor Deposition ; PECVD）成長850nm的SiO2絕緣層在矽晶圓表面，接續以上光阻（Coating Photoresis）、軟烤 （Soft Bake）、曝光（Exposure）、顯影（Development）等微影（Photoligraphy）製程定義後續所需之圖型，並使用直流磁控濺鍍系統（Magnetron Sputtering Deposition）沉積鈦（Ti）及鉑（Pt）的薄膜以製備下電極，厚度分別為40 / 200nm；使用射頻及直流磁控濺鍍系統分別沉積碲硒化鉍（Bi2.0Te2.7Se0.3）與碲銻化鉍（Bi0.4Te3.0Sb1.6）各1um以製備N極和P極熱電材料；最後再以直流磁控濺鍍系統沉積Ti / Pt薄膜以製備上電極，厚度分別為1500 / 500nm。

In this thesis, we create the 3D microthermoelectric cooler, which has the 3D micro structure, to promote P-N couples on the unit area and reduce the thermal conductivity to improve efficiency of the device. The whole process, including 21 steps of semiconductor manufacturing technology, has to use 5 masks, and Ti was compatible with all semiconductor manufacturing technology. This design will be helpful for the applicability of the device and the compatibility with other electrical devices. We used plasma enhanced chemical vapor deposition technique to provide electrical insulation for device. The 850nm silicon dioxide (SiO2) layer is grown on the Si wafer. Also, we used the photoligraphy process, including coating photoresis, soft bake, exposure and development, to definite the graph, and deposit the Ti/Pt thin film as the bottom of electrode by using DC magnetron sputtering deposition technique. The thickness of Ti and Pt layers are respectively 40nm and 200nm. Besides, we used RF and DC magnetron sputtering deposition technique to deposit 1um Bi2.0Te2.7Se0.3 and 1um Bi0.4Te3.0Sb1.6 as the N-type and P-type thermoelectric material. Finaly, DC magnetron sputtering deposition technique was used to deposit the Ti/Pt thin film as the top of electrode. The thickness of Ti and Pt layers are respectively 1500nm and 500nm.