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  1. NTU Theses and Dissertations Repository
  2. 工學院
  3. 機械工程學系
Please use this identifier to cite or link to this item: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/19307
Title: 固態化學氣相沉積二硫化鉬之鈀電極背閘極式場效電晶體特性研究
Characterization of MoS2 Back Gate FET by using Solid CVD with Pd Contact Electrode for Monolayer Ultra-Thin Body Transistor
Authors: Chia-Han Yeh
葉佳翰
Advisor: 廖洺漢(Ming-Han Liao)
Keyword: 二維材料,二硫化鉬,固態化學氣相沉積,掀離製程,金屬電極,背閘極式場效電晶體,
Two-dimensional material,Molybdenum disulfide,solid chemical vapor deposition,lift-off process,metal electrode,back gate field-effect transistor,
Publication Year : 2016
Degree: 碩士
Abstract: 本篇論文主要是針對近年來新興熱門的二維材料(2D material)-二硫化鉬(MoS2)作研究。由於二硫化鉬與金屬之間的介面有著很高的電阻值,因此針對這個問題去做發揮討論。我們以二硫化鉬作為通道,製作出背閘極式場效電晶體(back gate field effect transistor)。電極選用了鉑(Pt)、鈦(Ti)、鎢(W)、鈀(Pd)四種不同的金屬材料,利用元件電性上的表現,找出最適合的金屬電極,作為未來製作元件上的參考。
  在元件的製程上,目前主流沉積二硫化鉬薄膜的方式主要有三種,分別是剝離法(Exfoliate)、分子束磊晶法(Molecular beam epitaxy)、化學氣相沉積法(Chemical vapor deposition)。而我們選用了製程穩定且可以沉積大面積的化學氣相沉積法成長二硫化鉬薄膜,其層數約6~8層,厚度為0.63奈米。接著使用濺鍍機將以上四種金屬,濺鍍於元件上約150nm厚,元件的線寬(Gate length)約為微米等級,最後使用簡單且迅速的掀離製程(Lift-off process),將金屬附著於特定位置,完成整個背閘極式場效電晶體的製作。
  完成以上製程後,將元件拿去量測並繪製出Id-Vd與Id-Vg電性圖,比較不同金屬電極下的元件表現。鉑金屬在製程上良率極低,元件不易製作。鈦金屬則有部分元件能夠成功製作,但是電性表現不穩定。鎢金屬與鈀金屬良率不錯,成功率高,元件有明確的運作能力。而鈀金屬表現最佳,通道長度為10µm的二硫化鉬電晶體,在閘極偏壓為5V的狀況下,開啟電流可以達到7.94×10-7(A/µm)。除此之外,此元件的電流開關比大約可以達成3~4個數量級,有不錯的開關能力。因此鈀金屬在未來電極的應用上有著很大的發展空間。
In this thesis, we dedicate to the novel two-dimensional materials – MoS2. Owing to the high resistance interface between MoS2 and metal contact, we focus on this topic to discuss. MoS2 is used as channel material to fabricate the back gate field effect transistor.
By comparing the behavior between Pt, Ti, W and Pd metal contact, we analyze the electrical results and calculate the electrical performance to choose the best metal electrode we can use in the future.
  In the process of fabrication, there are three main methods to deposit MoS2 film -exfoliation, molecular beam epitaxy and chemical vapor deposition. Due to the fact that it is steady and has large area of deposition, we deposit the MoS2 film by chemical vapor deposition. It was about 6~8 layers, and the thickness is 0.63nm. Then, the deposition of the metal was done by sputter for thickness of 150nm. Gate length is in micro scale. At last, we use simple and quick lift-off process to complete the metal electrode. The back gate FET would be fabricated.
  After finishing the fabrication of the device, we measure the electrical results and illustrate the Id-Vd and Id-Vg electrical characteristic to compare the performance of the device. Since the yield is low with Pt electrode, it is hard to fabricate. Though the device can be partly fabricated with Ti electrode, the performance of device is poor. It is high yield with W and Pd electrode. They have great performance in device operation, especially Pd. In 10µm channel length, the on current can attain 7.94×10-7(A/µm) at 5V operation bias. The on/off ratio achieve 103~104. It has good ability in operation. Pd electrode has potential in application in the future.
URI: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/19307
DOI: 10.6342/NTU201601091
Fulltext Rights: 未授權
Appears in Collections:機械工程學系

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