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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 廖洺漢(Ming-Han Liao) | |
| dc.contributor.author | Chia-Han Yeh | en |
| dc.contributor.author | 葉佳翰 | zh_TW |
| dc.date.accessioned | 2021-06-08T01:53:00Z | - |
| dc.date.copyright | 2016-08-02 | |
| dc.date.issued | 2016 | |
| dc.date.submitted | 2016-07-19 | |
| dc.identifier.citation | [1] TIME Magazine, “The Year Man Becomes Immortal”, Feb. 10, 2011.
[2] W. Lerch, S. Paul, J. Niess, J. Chan, S. McCoy, J. Gelpey, F. Cristiano, F. Severac, P. F. Fazzini, D.Bolze, P. Pichler, A. Martinez, A. Mineji, S. Shishiguchi, “Experimental and theoretical results of dopant activation by a combination of spike and flash annealing”, Ext. Abs. the 7th International Workshop on Junction Technology, 2007 [3] International Technology Roadmap for Semiconductors, 2007. [4] H. M. Fahad and M. M. Hussain “Are Nanotube Architectures More Advantageous Than Nanowire Architectures For Field Effect Transistors?” Science, Vol. 475, p. 2012. [5] J. Treger, “A Peek at the Future-Intel’s Technology Roadmap,” Available: http://www.intel.com/content/www/us/en/it-managers/peek-at-the-future-rick-white-presentation.html. [6] B. Sheu, K. Wilcox, A. K. D. Antoniadis,” Moore’s Law Challenges Below 10nm: Technology Design and Economic Implications”, 2015. [7] Tutorials points simply easy learning, “VLSI Design – MOS Transistor” [8] A. Brand, SSG Transistor Technology Group,” Precision Material to Meet Scaling Challenges Beyond 14nm.” 2013. [9] A. K. Geim, I. V. Grigorieva, “Van der Waals heterostructures”, Nature, Vol. 499, p. 419-425, 2013. [10] Kateryna Shavanova, Yulia Bakakina, Inna Burkova, Ivan Shtepliuk, Roman Viter, Arnolds Ubelis, Valerio Beni, Nickolaj Starodub, Rositsa Yakimova and Volodymyr Khranovskyy, “Application of 2D Non-Graphene Materials and 2D Oxide Nanostructures for Biosensing Technology”, licensee MDPI, Basel, Switzerland, 2016. [11] Deji Akinwande, Nicholas Petrone & James Hone, “Two-dimensional flexible nanoelectronics”, Nature Communication. Review, Vol 5678, 2014. [12] Wiley Publishing, Nanotechnology For Dummies (2nd edition). [13] Shinichiro Mouri, Yuhei Miyauchi, and Kazunari Matsuda, “Tunable Photoluminescence of Monolayer MoS2 via Chemical Doping.” Nano Lett, Vol 13, 2013. [14] Eugene S. Kadantsev, Pawel Hawrylak. “Electronic structure of a single MoS2 monolayer” Solid State Communications, Vol 152, p. 909–913, 2012. [15] Haiwei Du, Xi Lin, Zhemi Xu, Dewei Chu. “Recent developments in black phosphorus transistors.” J. Mater. Chem. C, Vol 3, p. 8760—8775, 2015. [16] Zhike Liu, Shu Ping Lau and Feng Yan. “Functionalized graphene and other two-dimensional materials for photovoltaic devices: device design and processing” Chem. Soc. Vol 44, p. 5638—5679, 2015 [17] Gianluca Fiori1, Francesco Bonaccorso, Giuseppe Iannaccone, Tomas Palacios, Daniel Neumaier, Alan Seabaugh, Sanjay K. Banerjee, Luigi Colombo. “Electronics based on two-dimensional materials” Nature Nanotechnology, Vol 9, p. 768–779, 2014 [18] G.Fiori, G. Iannaccone. “The challenging promise of 2D Materials for Electronics.” IEEE, IEDM15 , p. 691-694, 2015. [19] K S Novoselov, A H Castro Neto. “Two-dimensional crystals-based heterostructures: materials with tailored properties” Physica Scripta., T146, 2012. [20] Andrew R. Barron. “Chemistry of Electronic Materials.” OpenStax-CNX, 2014. [21] Keng-Ku Liu, Wenjing Zhang, Yi-Hsien Lee, Yu-Chuan Lin, Mu-Tung Chang, Ching-Yuan Su, Chia-Seng Chang, Hai Li, Yumeng Shi, Hua Zhang, Chao-Sung Lai, Lain-Jong Li. “Growth of Large-Area and Highly Crystalline MoS2 Thin Layers on Insulating Substrates” Nano Letter, Vol 12, p. 1538−1544, 2012. [22] Han Liu, Mengwei Si, Sina Najmaei, Adam T. Neal, Yuchen Du, Pulickel M. Ajayan, Jun Lou, Peide D. Ye. “Statistical Study of Deep Submicron Dual-Gated Field-EffectTransis tors on Monolayer Chemical Vapor Deposition Molybdenum Disulfide Films” Nano Letter, Vol 13, p. 2640−2646, 2013. [23] Saptarshi Das, Hong-Yan Chen, Ashish Verma Penumatcha, and Joerg Appenzeller. “High Performance Multilayer MoS2 Transistors with Scandium Contacts” Nano Letter, Vol 13, p. 100−105, 2013. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/19307 | - |
| dc.description.abstract | 本篇論文主要是針對近年來新興熱門的二維材料(2D material)－二硫化鉬(MoS2)作研究。由於二硫化鉬與金屬之間的介面有著很高的電阻值，因此針對這個問題去做發揮討論。我們以二硫化鉬作為通道，製作出背閘極式場效電晶體(back gate field effect transistor)。電極選用了鉑(Pt)、鈦(Ti)、鎢(W)、鈀(Pd)四種不同的金屬材料，利用元件電性上的表現，找出最適合的金屬電極，作為未來製作元件上的參考。
在元件的製程上，目前主流沉積二硫化鉬薄膜的方式主要有三種，分別是剝離法(Exfoliate)、分子束磊晶法(Molecular beam epitaxy)、化學氣相沉積法(Chemical vapor deposition)。而我們選用了製程穩定且可以沉積大面積的化學氣相沉積法成長二硫化鉬薄膜，其層數約6~8層，厚度為0.63奈米。接著使用濺鍍機將以上四種金屬，濺鍍於元件上約150nm厚，元件的線寬(Gate length)約為微米等級，最後使用簡單且迅速的掀離製程(Lift-off process)，將金屬附著於特定位置，完成整個背閘極式場效電晶體的製作。 完成以上製程後，將元件拿去量測並繪製出Id-Vd與Id-Vg電性圖，比較不同金屬電極下的元件表現。鉑金屬在製程上良率極低，元件不易製作。鈦金屬則有部分元件能夠成功製作，但是電性表現不穩定。鎢金屬與鈀金屬良率不錯，成功率高，元件有明確的運作能力。而鈀金屬表現最佳，通道長度為10µm的二硫化鉬電晶體，在閘極偏壓為5V的狀況下，開啟電流可以達到7.94×10-7(A/µm)。除此之外，此元件的電流開關比大約可以達成3~4個數量級，有不錯的開關能力。因此鈀金屬在未來電極的應用上有著很大的發展空間。 | zh_TW |
| dc.description.abstract | In this thesis, we dedicate to the novel two-dimensional materials – MoS2. Owing to the high resistance interface between MoS2 and metal contact, we focus on this topic to discuss. MoS2 is used as channel material to fabricate the back gate field effect transistor.
By comparing the behavior between Pt, Ti, W and Pd metal contact, we analyze the electrical results and calculate the electrical performance to choose the best metal electrode we can use in the future. In the process of fabrication, there are three main methods to deposit MoS2 film -exfoliation, molecular beam epitaxy and chemical vapor deposition. Due to the fact that it is steady and has large area of deposition, we deposit the MoS2 film by chemical vapor deposition. It was about 6~8 layers, and the thickness is 0.63nm. Then, the deposition of the metal was done by sputter for thickness of 150nm. Gate length is in micro scale. At last, we use simple and quick lift-off process to complete the metal electrode. The back gate FET would be fabricated. After finishing the fabrication of the device, we measure the electrical results and illustrate the Id-Vd and Id-Vg electrical characteristic to compare the performance of the device. Since the yield is low with Pt electrode, it is hard to fabricate. Though the device can be partly fabricated with Ti electrode, the performance of device is poor. It is high yield with W and Pd electrode. They have great performance in device operation, especially Pd. In 10µm channel length, the on current can attain 7.94×10-7(A/µm) at 5V operation bias. The on/off ratio achieve 103~104. It has good ability in operation. Pd electrode has potential in application in the future. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T01:53:00Z (GMT). No. of bitstreams: 1 ntu-105-R03522625-1.pdf: 3836880 bytes, checksum: 6fc72493fa3dd9b56c289ab8273f125e (MD5) Previous issue date: 2016 | en |
| dc.description.tableofcontents | 目錄
口試委員會審定書 i 致謝 ii 中文摘要 iii ABSTRACT iv 目錄 v 圖目錄 vii 表目錄 ix 第一章 緒論 1 1.1 半導體元件之微縮極限 1 1.2 半導體元件之歷史背景 2 1.3 半導體元件之發展方向 4 1.4 論文架構 8 第二章 二維材料 9 2.1 二維材料的興起 9 2.2 二維材料的介紹 13 2.2.1 石墨烯(Graphene) 13 2.2.2 二硫化鉬(MoS2) 14 2.2.3 黑磷烯(Black Phosphrorene) 16 2.3 二維材料的比較 17 第三章 實驗製程步驟 22 3.1 二硫化鉬的薄膜成長 22 3.1.1 剝離法(exfoliation) 22 3.1.2 分子束磊晶(molecular beam epitaxy) 24 3.1.3 化學氣相沉積法(chemical vapor deposition) 25 3.1.4 二硫化鉬沉積方法比較 27 3.2 背閘極式電晶體元件的製程 28 3.2.1 利用化學氣相沉積成長二硫化鉬薄膜 28 3.2.2 掀離製程(Lift-off)成長電極 30 第四章 元件電性量測結果 38 4.1 電性圖繪製與分析 38 4.1.1 钛金屬電極背閘極式電晶體元件電性 39 4.1.2 鎢金屬電極背閘極式電晶體元件電性 40 4.1.3 鈀金屬電極背閘極式電晶體元件電性 41 第五章 結論與未來規劃 42 5.1 結論 42 5.2 未來展望 42 REFERENE 43 圖目錄 圖1.1 終端電子產品的歷史發展過程[1] 1 圖1.2 近年來邏輯處理器的功率密度成長情形[2] 2 圖1.3 摩爾定律下之半導體元件的演進[3][4][5] 3 圖1.4 摩爾定律下各世代電子元件的演進狀況[6] 4 圖1.5 基本場效電晶體的結構與運作[7] 5 圖1.6 汲極電流對閘極電壓作圖觀察DIBL效應 (a)長通道 (b)短通道 6 圖1.7 目前國際主流團隊針對未來電晶體元件架構的主流研究方向。[8] 7 圖2.1 二維材料異質結構堆疊[9] 10 圖2.2 二維材料分類表[9] 11 圖2.3 二維材料元件可撓性之生活應用[11] 12 圖2.4 石墨烯結構圖[12] 13 圖2.5 過度金屬硫族化物結構圖[13] 14 圖2.6 二硫化鉬晶格結構圖[14] 15 圖2.7 磷烯結構圖[15] 16 圖2.8 (a)單層石墨烯、(b)二硫化鉬、(c)黑磷的電子能帶圖[15] 17 圖2.9 材料特性比較 (a)載子遷移率與開關比 (b)振盪頻率與輸出功率電壓[16] 19 圖2.10 二維材料之動態功率指標與電晶體切換之延遲時間和ITRS趨勢[18] 21 圖3.1 機械剝離法示意圖[19] 22 圖3.2 化學剝離法示意圖[19] 23 圖3.3 分子束磊晶示意圖[20] 24 圖3.4 利用四硫鉬酸銨沉積二硫化鉬示意圖[21] 25 圖3.5 利用硫粉末與三氧化鉬沉積二硫化鉬示意圖[22] 26 圖3.6 化學氣相沉積二硫化鉬實驗示意圖 29 圖3.7 二硫化鉬沉積腔體內溫度變化 29 圖3.8 穿透式電子顯微鏡下之二硫化鉬 30 圖3.9 曝光微影流程圖 30 圖3.10 試片旋轉塗佈 31 圖3.11 試片軟烤 32 圖3.12 試片曝光 32 圖3.13 顯影後顯微鏡下的圖形 33 圖3.14 用兩層光阻曝光後的情形 35 圖3.15 掀離製程的製作流程示意圖 37 圖4.1 顯微鏡下元件完成圖 38 圖4.2 元件完成品示意圖 38 圖4.3 鈦電極元件電性結果圖 39 圖4.4 鎢電極元件電性結果圖 40 圖4.5 鈀電極元件電性結果圖 41 表目錄 表2.1 三維與二維材料的比較 9 表2.2 二維材料光學、電學、機械、熱學特性比較[11] 12 表2.3 常見半導體材料載子遷移率和能帶差的數值 18 表3.1 剝離法、分子束磊晶法、分子束磊晶法、化學氣相沉積法比較 27 表3.2 二硫化鉬沉積參數 28 表3.3 光阻旋轉塗佈參數 34 表3.4 濺鍍金屬分別的參數 36 表4.1 鈦電極元件電性結果 39 表4.2 鎢電極元件電性結果 40 表4.3 鈀電極元件電性結果 41 | |
| dc.language.iso | zh-TW | |
| dc.title | 固態化學氣相沉積二硫化鉬之鈀電極背閘極式場效電晶體特性研究 | zh_TW |
| dc.title | Characterization of MoS2 Back Gate FET by using Solid CVD with Pd Contact Electrode for Monolayer Ultra-Thin Body Transistor | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 104-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 陳旻政(Min-Cheng Chen),李愷信(Kai-Shin Li),李敏鴻(Min-Hung Lee) | |
| dc.subject.keyword | 二維材料,二硫化鉬,固態化學氣相沉積,掀離製程,金屬電極,背閘極式場效電晶體, | zh_TW |
| dc.subject.keyword | Two-dimensional material,Molybdenum disulfide,solid chemical vapor deposition,lift-off process,metal electrode,back gate field-effect transistor, | en |
| dc.relation.page | 45 | |
| dc.identifier.doi | 10.6342/NTU201601091 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2016-07-20 | |
| dc.contributor.author-college | 工學院 | zh_TW |
| dc.contributor.author-dept | 機械工程學研究所 | zh_TW |
| 顯示於系所單位： | 機械工程學系 | |
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