具寄生電容補償電路之十位元連續漸進式類比數位轉換器

Abstract

連續漸進式類比數位轉換器(Successive approximation register analog-to-digital converters)是一個以二位元搜尋的方式實現的轉換器。此架構廣泛的運用於低功耗和低速的應用。而近年來，在製程逐漸進步下，電晶體的線寬越來越小，連續漸進式類比數位轉換器逐漸可運用於中功耗和中速度的應用。但是在線寬越來越小的情況下，寄生電容的影響也逐漸變大。 本論文實踐一個十位元20 MS/s 的連續漸進式類比數位轉換器，以單調電容器切換程序(monotonic capacitor switching procedure)運行，並添加一個寄生電容補償電路來減小寄生電容的影響。在T18製程下，實踐一顆有效輸出位元(ENOB)為9.07，FoM為171.1 fJ/conv.step的類比數位轉換器。

A successive approximation register (SAR) analog-to-digital converter (ADC) is using a binary search through all possible quantization levels before finally converging upon a digital output for each conversion. SAR architecture is extensively used in low-power and low-speed applications. However, with the feature size of CMOS devices scaled down in recent years, SAR ADCs have achieved a medium speed with a medium resolution. But in the same time, the parasitic capacitance becomes an issue when the feature size of a circuit becomes smaller and smaller. This Thesis presents the design of a low-power 10-bit 20-MS/s successive approximation register analog-to-digital converter that uses a monotonic capacitor switching procedure and parasitic capacitance compensation circuits to reduce the impact of parasitic capacitances. The prototype was fabricated in T18 technology. The effective number of bits (ENOB) was 9.07, and Figure of merit (FoM) was 171.1 fJ/conv.step.