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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳少傑 | |
dc.contributor.author | Tai-Hsin Ou | en |
dc.contributor.author | 歐岱鑫 | zh_TW |
dc.date.accessioned | 2021-06-08T01:38:30Z | - |
dc.date.copyright | 2017-02-08 | |
dc.date.issued | 2016 | |
dc.date.submitted | 2016-09-05 | |
dc.identifier.citation | [1] L.-J. McCreary and P.-R. Gray, 'All-MOS Charge Redistribution Analog-to-Digital ConversionTechniques,' IEEE Journal of Solid-State Circuits, vol.10, no.6, pp.371-379, October 1975.
[2] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, 'A 10-bit 50-MS/s SAR ADC with a Monotonic Capacitor Switching Procedure,' IEEE Journal of Solid-State Circuits, vol.45, no.4, pp.731-740, April 2010. [3] A.-M. Abo and P.-R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE Journal of Solid-State Circuits, vol.34, no.5, pp. 599-606, May 1999. [4] S. Jiang, M.-A. Do, K.-S. Yeo, and W.-M. Lim, “An 8-bit 200-MSamples/s Pipelined ADC with Mixed-mode Front-end S/H Circuit,” IEEE Transactions on Circuits and Systems, vol.55, no.6, pp.1430-1440, July 2008. [5] J.-R. Yuan, S. Christer, “A True Single-Phase-Clock Dynamic CMOS Circuit Technique,” IEEE Journal of Solid-State Circuits, vol.24, no.5, pp.62-70, February 1989. [6] P. J. A. Harpe, C. Zhou, Y. Bi, N.P. van der Meijs, X. Wang, K. Philips, G. Dolmans, and H. de Groot, 'A 26 W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios,' IEEE Journal of Solid-State Circuits, vol.46, no.7, pp.1585-1595, July 2011. [7] J.-Y. Lin and C.-C. Hsieh, 'A 0.3 V 10-bit 1.17 f SAR ADC with Merge and Split Switching in 90 nm CMOS,' IEEE Transactions on Circuits and Systems, vol.62, no.1, pp.70-79, January 2015. [8] Z. Zhu, Z. Qiu, 'A 6-to-10-Bit 0.5 V-to-0.9 V Reconfigurable 2 MS/s Power Scalable SAR ADC in 0.18 CMOS,' IEEE Transactions on Circuits and Systems, vol.62, no.3, pp.689-696, March 2015. [9] L. Sun and B. Li 'A Charge Recycling SAR ADC with a LSB-down Switching Scheme,' IEEE Transactions on Circuits and Systems, vol.62, no.2, pp.356-365, February 2015. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18886 | - |
dc.description.abstract | 連續漸進式類比數位轉換器(Successive approximation register analog-to-digital converters)是一個以二位元搜尋的方式實現的轉換器。此架構廣泛的運用於低功耗和低速的應用。而近年來,在製程逐漸進步下,電晶體的線寬越來越小,連續漸進式類比數位轉換器逐漸可運用於中功耗和中速度的應用。但是在線寬越來越小的情況下,寄生電容的影響也逐漸變大。
本論文實踐一個十位元20 MS/s 的連續漸進式類比數位轉換器,以單調電容器切換程序(monotonic capacitor switching procedure)運行,並添加一個寄生電容補償電路來減小寄生電容的影響。在T18製程下,實踐一顆有效輸出位元(ENOB)為9.07,FoM為171.1 fJ/conv.step的類比數位轉換器。 | zh_TW |
dc.description.abstract | A successive approximation register (SAR) analog-to-digital converter (ADC) is using a binary search through all possible quantization levels before finally converging upon a digital output for each conversion. SAR architecture is extensively used in low-power and low-speed applications. However, with the feature size of CMOS devices scaled down in recent years, SAR ADCs have achieved a medium speed with a medium resolution. But in the same time, the parasitic capacitance becomes an issue when the feature size of a circuit becomes smaller and smaller.
This Thesis presents the design of a low-power 10-bit 20-MS/s successive approximation register analog-to-digital converter that uses a monotonic capacitor switching procedure and parasitic capacitance compensation circuits to reduce the impact of parasitic capacitances. The prototype was fabricated in T18 technology. The effective number of bits (ENOB) was 9.07, and Figure of merit (FoM) was 171.1 fJ/conv.step. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T01:38:30Z (GMT). No. of bitstreams: 1 ntu-105-R02943123-1.pdf: 5580869 bytes, checksum: 2376d93315c790f00234f497adba6c52 (MD5) Previous issue date: 2016 | en |
dc.description.tableofcontents | TABLE OF CONTENTS
ABSTRACT i LIST OF FIGURES v LIST OF TABLES vii CHAPTER 1 INTRODUCTION 1 1.1 Motivation 1 1.2 Thesis Organization 2 CHAPTER 2 BACKGROUND 5 2.1 Quantization Noise 5 2.2 Static Performance Metrics 7 2.2.1 Differential Nonlinearity 8 2.2.2 Integral Nonlinearity 8 2.2.3 Offset Error 9 2.2.4 Gain Error 10 2.3 Dynamic Performance Metrics 11 2.3.1 Signal-to-Noise Ratio 11 2.3.2 Total Harmonic Distortion 11 2.3.3 Spurious Free Dynamic Range 12 2.3.4 Signal-to-Noise and Distortion Ratio 12 2.3.5 Effective Number of Bits 13 CHAPTER 3 CONVENTIONAL SAR ADC 15 3.1 Conventional SAR ADC Architecture 15 3.2 Conventional SAR ADC Algorithm 16 3.3 Conventional Switching Procedure 17 3.4 Charge Redistribution Method 20 CHAPTER 4 MODIFIED SAR ADC 23 4.1 Modified SAR ADC Architecture 23 4.2 Modified SAR ADC Algorithm 24 4.3 Modified Switching Procedure 25 4.4 Building Blocks of Modified SAR ADC 27 4.4.1 Bootstrapped Switch 33 4.4.2 Dynamic Comparator 34 4.4.3 Asynchronous Control Logic 35 CHAPTER 5 IMPLEMENTATION AND RESULTS 39 5.1 Capacitor Array and Layout Floorplan 39 5.2 Pre-simulation Results 41 5.3 Post-simulation Results 44 CHAPTER 6 CONCLUSION 47 REFERENCE 49 | |
dc.language.iso | en | |
dc.title | 具寄生電容補償電路之十位元連續漸進式類比數位轉換器 | zh_TW |
dc.title | A 10-BIT Successive Approximation Register ADC with a Parasitic Capacitance Compensation Circuit | en |
dc.type | Thesis | |
dc.date.schoolyear | 105-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 游竹,陳中平,林伯星 | |
dc.subject.keyword | 連續漸進式類比數位轉換器,寄生電容補償電路,單調電容器切換程序, | zh_TW |
dc.subject.keyword | Successive approximation register Analog-to-digital converter,parasitic capacitance compensation circuits,monotonic capacitor switching procedure, | en |
dc.relation.page | 50 | |
dc.identifier.doi | 10.6342/NTU201603574 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2016-09-05 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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