鍺及鍺錫合金之金氧半電容製備與特性分析

Abstract

隨著摩爾定律的推進，半導體元件的尺寸持續地因工業技術精進而微縮，但傳統的矽金氧半場效電晶體技術已經逐漸達到其微縮的極限。為了要突破物理極限以維持元件微縮的步調，必須要開發更高載子遷移率的新穎材料來取代傳統矽作為元件通道材料，因此鍺或是鍺錫的高載子遷移率材料相當受到矚目。在此篇論文中，我們對鍺與鍺錫的金氧半電容元件(MISCAPs)進行製備及電性分析。 本論文中，我們利用快速熱氧化法來成長二氧化鍺作為鍺與高介電係數材料的介面層並接著使用原子層沉積來生長高介電係數材料三氧化二鋁。我們使用電容量測及低溫電導法得知金氧半鍺電容的電性表現。當以二氧化鍺作為介面層時，介面缺陷密度約為10^12 cm-2eV-1；而當介面層為氧化鋁鍺時，則能降低介面缺陷密度至約10^11 cm-2eV-1。我們成功利用沉積整層的鋁並使用濕蝕刻的方法製作了包含氧化鋁鍺介面層及不同上電極金屬的金氧半電容元件。 接著我們利用氧化鋁鍺作為介面層製作鍺錫電容元件，並利用Ｘ射線光譜、原子力顯微鏡及Ｘ射線繞熱分析鍺錫材料的熱積存問題，定義出最適當的製程溫度應低於攝氏350 度。 我們利用電容量測中出現的遲滯現象去分析探討氧化鋁鍺的可靠度，利用不同的電壓應力時間來分析，發現由於氧化鋁鍺的氧化層缺陷較少，因此其遲滯現象(218mV)較二氧化鍺(297mV)來的不明顯，並且在經過氮氫混合氣熱退火後，能更進一步降低氧化鋁鍺的氧化層缺陷數量。 最後，我們利用二氧化鉻與三氧化二鋁氧化層製作電容，其有效氧化層厚度能達到0.8 奈米並維持約10^12cm-2eV-1 的介面缺陷密度，我們並將這個結果應用在無接面赭環繞式閘極場效電晶體上，其汲極電流為828μA/μm。我們並利用ANSYS軟體分析得知鍺通道的拉伸應變為0.25%

Recently, semiconductor industry technology has followed the path of scaling trend based on Moore’s Law. But conventional planar Si MOSFETs is approaching its fundamental scaling limits. For the continuation of the scaling trend, high mobility materials have been comprehensively investigated as channel material for replacing Si, Ge or GeSn are candidate materials due to its high intrinsic carrier mobility. In this thesis, the fabrication and electrical characterization of germanium (Ge) and germanium-tin alloy (GeSn) Metal-Insulator-Semiconductor Capacitances (MISCAPs) are investigated. In the first of this thesis, rapid thermal oxidation (RTO) is used as an effective way to growth GeO2 interfacial layer to passivate Ge channel and Al2O3 as high-k layer is deposited by atomic-layer-deposition (ALD). The CV characterizations of Ge MISCAPs and the interface trap density extracted by low-temperature conductance method are measured. The MISCAPs with AlGeO interfacial layer has lower interface trap density (Dit) (~10^11cm-2eV-1) than that with GeO2 IL(~10^12cm-2eV-1). The MISCAPs with good quality AlGeO interfacial layer and replaceable work function metal is realized by wet etching of Al film deposited on Al2O3. In the second part of the thesis, GeSn MISCAPs is fabricated with AlGeO interfacial layer. The highest process temperature is limited at 350oC due to the thermal budget of metastable GeSn alloy, which is figured out by the EDX, AFM and XRD of GeSn MISCAPs with different growth temperature. The reliability of AlGeO interfacial layer is analyzed by measuring the hysteresis of C-V characteristic with different constant voltage stress times. The hysteresis of AlGeO (218mV) is lower than GeO2 (297mV) due to the lower border trap density in AlGeO layer. The Hysteresis and flat-band shift of AlGeO can be improved by forming gas annealing (FGA). In the last of this thesis, low-EOT MISCAPs with TiN/ZrO2/Al2O3/Ge gate stack is fabricated with EOT of 0.8nm and Dit of about 10^12cm-2eV-1. The gate stack is used on junctionless Ge gate-all-around FETs with drive current of 828μA/μm. The tensile strain of Ge channel is 0.25% simulated by ANSYS.