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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17885完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉致為(Chee-Wee Liu) | |
| dc.contributor.author | Tzu-Yao Lin | en |
| dc.contributor.author | 林子堯 | zh_TW |
| dc.date.accessioned | 2021-06-08T00:45:26Z | - |
| dc.date.copyright | 2015-08-05 | |
| dc.date.issued | 2015 | |
| dc.date.submitted | 2015-08-03 | |
| dc.identifier.citation | chapter 1
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[31] Kita, K., et al. 'Comprehensive study of GeO 2 oxidation, GeO desorption and GeO 2-metal interaction-understanding of Ge processing kinetics for perfect interface control.' Electron Devices Meeting (IEDM), 2009 IEEE International. IEEE, 2009. [32] Molle, Alessandro, et al. 'Formation and stability of germanium oxide induced by atomic oxygen exposure.' Materials science in semiconductor processing9.4 (2006): 673-678. [33] Baldovino, Silvia, Alessandro Molle, and Marco Fanciulli. 'Influence of the oxidizing species on the Ge dangling bonds at the (100) Ge/GeO2 interface.'Applied physics letters 96.22 (2010): 2110. [34] Oniki, Yusuke, et al. 'Evaluation of GeO desorption behavior in the metal/GeO2/Ge structure and its improvement of the electrical characteristics.'Journal of applied physics 107.12 (2010): 124113. [35] Chui, Chi On, et al. 'Activation and diffusion studies of ion-implanted p and n dopants in germanium.' Applied physics letters 83.16 (2003): 3275-3277. chapter 3 [1] Lan, H-S., and C. W. Liu. 'Ballistic electron transport calculation of strained germanium-tin fin field-effect transistors.' Applied Physics Letters 104.19 (2014): 192101. [2] Sau, Jay Deep, and Marvin L. Cohen. 'Possibility of increased mobility in Ge-Sn alloy system.' Physical Review B 75.4 (2007): 045208. [3] Roucka, R., et al. 'Versatile buffer layer architectures based on Ge1− xSnx alloys.' Applied Physics Letters 86.19 (2005): 191912. [4] Takeuchi, Shotaro, et al. 'Growth and structure evaluation of strain-relaxed Ge1−xSnx buffer layers grown on various types of substrates.' Semiconductor science and technology 22.1 (2007): S231. [5] Vincent, Benjamin, et al. 'Characterization of GeSn materials for future Ge pMOSFETs source/drain stressors.' Microelectronic Engineering 88.4 (2011): 342-346. [6] Eneman, Geert, et al. 'Stress simulations for optimal mobility group IV p-and nMOS FinFETs for the 14 nm node and beyond.' Electron Devices Meeting (IEDM), 2012 IEEE International. IEEE, 2012. [7] Chen, Robert, et al. 'Increased photoluminescence of strain-reduced, high-Sn composition Ge1-xSnx alloys grown by molecular beam epitaxy.' Applied Physics Letters 99.18 (2011): 181125. [8] Wang, Wei, et al. 'Thermal stability of highly compressive strained germaniumtin (GeSn) grown by molecular beam epitaxy.' Silicon-Germanium Technology and Device Meeting (ISTDM), 2014 7th International. IEEE, 2014. [9] Merckling, Clement, et al. 'Molecular beam deposition of Al2O3 on p-Ge (001)/Ge0.95Sn0.05 heterostructure and impact of a Ge-cap interfacial layer.' Applied Physics Letters 98.19 (2011): 192110-192110. [10] Currie, M. T., et al. 'Controlling threading dislocation densities in Ge on Si using graded SiGe layers and chemical-mechanical polishing.' Applied Physics Letters 72.14 (1998): 1718-1720. [11] Luan, Hsin-Chiao, et al. 'High-quality Ge epi-layers on Si with low threadingdislocation densities.' Applied Physics Letters 75.19 (1999): 2909-2911. [12] Brammertz, G., Alian, A., Lin, D. C., Meuris, M., Caymax, M., & Wang, W. E. (2011). A Combined Interface and Border Trap Model for High-Mobility Substrate Metal–Oxide–Semiconductor Devices Applied to and InP Capacitors.Electron Devices, IEEE Transactions on, 58(11), 3890-3897. [13] Lin, D., Alian, A., Gupta, S., Yang, B., Bury, E., Sioncke, S., ... & Thean, A. (2012, December). Beyond interface: The impact of oxide border traps on InGaAs and Ge n-MOSFETs. In Electron Devices Meeting (IEDM), 2012 IEEE International (pp. 28-3). IEEE. [14] Li, H., Cui, Y. X., Wu, K. Y., Tseng, W. K., Cheng, H. H., & Chen, H. (2013). Strain relaxation and Sn segregation in GeSn epilayers under thermal treatment. Applied Physics Letters, 102(25), 251907. [15] Chen, Robert, et al. 'Material characterization of high Sn-content, compressivelystrained GeSn epitaxial films after rapid thermal processing. 'Journal of Crystal Growth 365 (2013): 29-34. [16] Li, H., et al. 'Strain relaxation and Sn segregation in GeSn epilayers under thermal treatment.' Applied Physics Letters 102.25 (2013): 251907. chapter 4 [1] Lo, S. H., et al. 'Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's.' Electron Device Letters, IEEE 18.5 (1997): 209-211. [2] DiMaria, D. J., and J. H. Stathis. 'Ultimate limit for defect generation in ultrathin silicon dioxide.' Applied physics letters 71.22 (1997): 3230-3232. [3] Wilk, Glen D., Robert M. Wallace, and J. M. Anthony. 'High-κ gate dielectrics: Current status and materials properties considerations.' Journal of applied physics 89.10 (2001): 5243-5275. [4] Zafar, S., E. Cartier, and E. P. Gusev. 'Measurement of barrier heights in high permittivity gate dielectric films.' Applied physics letters 80 (2002): 2749. [5] Zhu, W. J., et al. 'Charge trapping in ultrathin hafnium oxide.' Electron Device Letters, IEEE 23.10 (2002): 597-599. [6] Zafar, Sufi, et al. 'Impact of moisture on charge trapping and flatband voltage in Al2O3 gate dielectric films.' Applied physics letters 81.14 (2002): 2608-2610. [7] Houssa, Michel, et al. 'Electrical properties of high-κ gate dielectrics: Challenges, current issues, and possible solutions.' Materials Science and Engineering: R: Reports 51.4 (2006): 37-85. [8] Bai, W. P., et al. 'Ge MOS characteristics with CVD HfO2 gate dielectrics and TaN gate electrode.' VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on. IEEE, 2003. [9] Huang, C. H., et al. 'Very low defects and high performance Ge-on-insulator p-MOSFETs with Al2O3gate dielectrics.' VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on. IEEE, 2003. [10] Chui, Chi On, et al. 'A sub-400/spl deg/C germanium MOSFET technology with high-/spl kappa/dielectric and metal gate.' Electron Devices Meeting, 2002. IEDM'02. International. IEEE, 2002. [11] Yusuke Oniki, Hideo Koumo, Yoshitaka Iwazaki, and Tomo Ueno, “Evaluation of GeO desorption behavior in the metal/ GeO2 / Ge structure and its improvement of the electrical characteristics,” Journal of Applied Physics 107, 124113 (2010). [12] Sugawara, Takuya, et al. 'Electrical properties of germanium/metal-oxide gate stacks with atomic layer deposition grown hafnium-dioxide and plasmasynthesized interface layers.' Applied physics letters 90.11 (2007): 2912. [13] Takagi, S., et al. 'Gate dielectric formation and MIS interface characterization on Ge.' Microelectronic engineering 84.9 (2007): 2314-2319. [14] Fleetwood, D. M., and N. S. Saks. 'Oxide, interface, and border traps in thermal, N2O, and N2O‐nitrided oxides.' Journal of applied physics 79.3 (1996): 1583- 1594. [15] Cohen, Neil L., Ronald E. Paulsen, and Marvin H. White. 'Observation and characterization of near-interface oxide traps with CV techniques.' Electron Devices, IEEE Transactions on 42.11 (1995): 2004-2009. [16] Zafar, Sufi, et al. 'Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks.' Journal of Applied physics 93 (2003): 9298-9303. [17] Nguyen, N. V., et al. 'Band offsets of atomic-layer-deposited Al2O3 on GaAs and the effects of surface treatment.' (2008). [18] Lin, L., K. Xiong, and J. Robertson. 'Atomic structure, electronic structure, and band offsets at Ge: GeO: GeO2 interfaces.' Applied Physics Letters 97.24 (2010): 2902. [19] Swaminathan, Shankar, et al. 'Ultrathin ALD-Al2O3 layers for Ge (001) gate stacks: Local composition evolution and dielectric properties.' Journal of Applied Physics 110.9 (2011): 094105. [20] Kim, Eun Ji, et al. 'Border traps in Al2O3/In0. 53Ga0. 47As (100) gate stacks and their passivation by hydrogen anneals.' Applied Physics Letters 96.1 (2010): 2906. chapter 5 [1] Auth, Chris, et al. 'A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors.' VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012. [2] Singh, N., et al. 'High-performance fully depleted silicon nanowire (diameter/spl les/5 nm) gate-all-around CMOS devices.' Electron Device Letters, IEEE 27.5 (2006): 383-386. [3] Yee, Yee Chia, et al. 'Nanoscale ultra-thin-body silicon-on-insulator PMOSFET with a SiGe/Si heterostructure channel.' Electron Device Letters, IEEE 21.4 (2000): 161-163. [4] Y. Kamata, Y. Kamimuta, T. Ino, and A. Nishiyama, Jpn. J. Appl. Phys., Part 1 44, 2323 (2005). [5] C. O. Chui, D. -I. Lee, A. A. Singh, P. A. Pianetta, and K. C. Saraswat, J. Appl.Phys. 97, 113518 (2005). [6] P. Tsipas, S. N. Volkos, A. Sotiropoulos, S. F. Galata, G. Mavrou, D. Tsoutsou, Y. Panayiotatos, A. Dimoulas, C. Marchiori, and J. Fompeyrine, Appl. Phys. Lett. 93, 082904 (2008). [7] Lin, Cheng-Ming, et al. 'Interfacial layer reduction and high permittivity tetragonal ZrO2 on germanium reaching ultrathin 0.39 nm equivalent oxide thickness.' Applied Physics Letters 102.23 (2013): 232906. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17885 | - |
| dc.description.abstract | 隨著摩爾定律的推進，半導體元件的尺寸持續地因工業技術精進而微縮，但傳統的矽金氧半場效電晶體技術已經逐漸達到其微縮的極限。為了要突破物理極限以維持元件微縮的步調，必須要開發更高載子遷移率的新穎材料來取代傳統矽作為元件通道材料，因此鍺或是鍺錫的高載子遷移率材料相當受到矚目。在此篇論文中，我們對鍺與鍺錫的金氧半電容元件(MISCAPs)進行製備及電性分析。
本論文中，我們利用快速熱氧化法來成長二氧化鍺作為鍺與高介電係數材料的介面層並接著使用原子層沉積來生長高介電係數材料三氧化二鋁。我們使用電容量測及低溫電導法得知金氧半鍺電容的電性表現。當以二氧化鍺作為介面層時，介面缺陷密度約為10^12 cm-2eV-1；而當介面層為氧化鋁鍺時，則能降低介面缺陷密度至約10^11 cm-2eV-1。我們成功利用沉積整層的鋁並使用濕蝕刻的方法製作了包含氧化鋁鍺介面層及不同上電極金屬的金氧半電容元件。 接著我們利用氧化鋁鍺作為介面層製作鍺錫電容元件，並利用Ｘ射線光譜、原子力顯微鏡及Ｘ射線繞熱分析鍺錫材料的熱積存問題，定義出最適當的製程溫度應低於攝氏350 度。 我們利用電容量測中出現的遲滯現象去分析探討氧化鋁鍺的可靠度，利用不同的電壓應力時間來分析，發現由於氧化鋁鍺的氧化層缺陷較少，因此其遲滯現象(218mV)較二氧化鍺(297mV)來的不明顯，並且在經過氮氫混合氣熱退火後，能更進一步降低氧化鋁鍺的氧化層缺陷數量。 最後，我們利用二氧化鉻與三氧化二鋁氧化層製作電容，其有效氧化層厚度能達到0.8 奈米並維持約10^12cm-2eV-1 的介面缺陷密度，我們並將這個結果應用在無接面赭環繞式閘極場效電晶體上，其汲極電流為828μA/μm。我們並利用ANSYS軟體分析得知鍺通道的拉伸應變為0.25% | zh_TW |
| dc.description.abstract | Recently, semiconductor industry technology has followed the path of scaling trend based on Moore’s Law. But conventional planar Si MOSFETs is approaching its fundamental scaling limits. For the continuation of the scaling trend, high mobility materials have been comprehensively investigated as channel material for replacing Si, Ge or GeSn are candidate materials due to its high intrinsic carrier mobility. In this thesis, the fabrication and electrical characterization of germanium (Ge) and germanium-tin alloy (GeSn) Metal-Insulator-Semiconductor Capacitances (MISCAPs) are investigated.
In the first of this thesis, rapid thermal oxidation (RTO) is used as an effective way to growth GeO2 interfacial layer to passivate Ge channel and Al2O3 as high-k layer is deposited by atomic-layer-deposition (ALD). The CV characterizations of Ge MISCAPs and the interface trap density extracted by low-temperature conductance method are measured. The MISCAPs with AlGeO interfacial layer has lower interface trap density (Dit) (~10^11cm-2eV-1) than that with GeO2 IL(~10^12cm-2eV-1). The MISCAPs with good quality AlGeO interfacial layer and replaceable work function metal is realized by wet etching of Al film deposited on Al2O3. In the second part of the thesis, GeSn MISCAPs is fabricated with AlGeO interfacial layer. The highest process temperature is limited at 350oC due to the thermal budget of metastable GeSn alloy, which is figured out by the EDX, AFM and XRD of GeSn MISCAPs with different growth temperature. The reliability of AlGeO interfacial layer is analyzed by measuring the hysteresis of C-V characteristic with different constant voltage stress times. The hysteresis of AlGeO (218mV) is lower than GeO2 (297mV) due to the lower border trap density in AlGeO layer. The Hysteresis and flat-band shift of AlGeO can be improved by forming gas annealing (FGA). In the last of this thesis, low-EOT MISCAPs with TiN/ZrO2/Al2O3/Ge gate stack is fabricated with EOT of 0.8nm and Dit of about 10^12cm-2eV-1. The gate stack is used on junctionless Ge gate-all-around FETs with drive current of 828μA/μm. The tensile strain of Ge channel is 0.25% simulated by ANSYS. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T00:45:26Z (GMT). No. of bitstreams: 1 ntu-104-R02943060-1.pdf: 5713105 bytes, checksum: 9759f1c7cf10da1d2b1e22ab7b08d291 (MD5) Previous issue date: 2015 | en |
| dc.description.tableofcontents | 口試委員會審定書 ...........................................................................................................#
中文摘要 .......................................................................................................................... ii ABSTRACT .................................................................................................................... iii CONTENTS ......................................................................................................................v LIST OF FIGURES....................................................................................................... viii LIST OF TABLES.......................................................................................................... xii Chapter 1 Introduction..............................................................................................1 1.1 Background and Motivation ...........................................................................1 1.2 Thesis Organization ........................................................................................4 1.3 Reference ........................................................................................................5 Chapter 2 Low Dit interfacial layer of AlGeO on Ge ..............................................6 2.1 Introduction.....................................................................................................6 2.2 Ge Interface Engineering................................................................................7 2.2.1 Ge Surface Preparation .........................................................................7 2.2.2 MISCAPs fabrication ............................................................................8 2.3 Electrical analysis and TEM of MISCAPs .....................................................9 2.3.1 C-V characteristics of MISCAPs ..........................................................9 2.3.2 Formation model of AlGeO ................................................................11 2.3.3 Interface trap densities (Dit) extraction ...............................................12 2.4 Al removed sample with AlGeO interfacial layer ........................................17 2.4.1 Fabrication of Al removed sample ......................................................17 2.4.2 Electrical properties of Al-removed MISCAPs...................................18 2.4.3 Edge effect of MISCAPs with AGO IL ..............................................20 2.5 MISCAPs with low thermal budget..............................................................22 2.5.1 Issues of Ge thermal budget ................................................................22 2.5.2 C-V characteristic analysis of MISCAPs with lower thermal budget.23 2.5.3 Fabrication and C-V characteristic of removed-Al sample.................29 2.6 Summary.......................................................................................................32 2.7 Reference ......................................................................................................32 Chapter 3 Fabrication and characterization of GeSn MISCAPs ........................37 3.1 Introduction...................................................................................................37 3.2 MISCAPs fabrication and C-V characteristics analysis ...............................38 3.2.1 Sample structure and analysis .............................................................38 3.2.2 Fabrication and C-V characteristic of GeSn MISCAPs......................40 3.3 MISCAPs with RTO at multi-temperature ...................................................46 3.4 Summary.......................................................................................................48 3.5 Reference ......................................................................................................48 Chapter 4 PBTI and hysteresis analysis of Ge based MISCAPs .........................51 4.1 Introduction...................................................................................................51 4.2 Hysteresis models and experiments..............................................................52 4.3 Flat-band voltage shift with constant voltage stress .....................................55 4.4 Hysteresis reduction by FGA........................................................................62 4.5 Summary.......................................................................................................65 4.6 Reference ......................................................................................................65 Chapter 5 Low-EOT gate stack and strain analysis for Junctionless Ge nGAAFETs .............................................................................................68 5.1 Introduction...................................................................................................68 5.2 MISCAPs fabrication and GAA device performance...................................69 5.3 Summary.......................................................................................................71 5.4 Reference ......................................................................................................71 Chapter 6 Summary and future work....................................................................73 6.1 Summary.......................................................................................................73 6.2 Future work...................................................................................................74 Appendix 75 Strain simulation and analysis for GAA structure ...................................................75 | |
| dc.language.iso | en | |
| dc.title | 鍺及鍺錫合金之金氧半電容製備與特性分析 | zh_TW |
| dc.title | Fabrication and Characterization of Ge and GeSn
MISCAPs | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 103-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李敏鴻(Min-Hung Lee),張書通(Shu-Tong chang),林吉聰(Chi-Tsung Lin),劉國辰(Kou-Chen Liu) | |
| dc.subject.keyword | 鍺,鍺錫,金氧半電容,氧化鋁鍺,介面缺陷密度,遲滯效應,應變, | zh_TW |
| dc.subject.keyword | Ge,GeSn,MISCAPs,AlGeO,interface trap density,hysteresis,strain, | en |
| dc.relation.page | 76 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2015-08-03 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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