毫米波放大器與矽基板整合玻璃基板之壓控震盪器之研究與分析

Abstract

放大器與電壓控制震盪器在現代的無線通訊中扮演著不可或缺的角色，本論文的重心在於此兩種電路的設計與分析。由於製程科技的演進，互補式金氧半導體(CMOS)可操作的頻率也逐漸升高，再加上其低成本與系統整合的優勢，讓原本以三五族半導體製程為主的微波毫米波電路也開始使用CMOS製程來設計與製造。本論文總共研究了三個電路，分別是使用了65奈米CMOS製程設計並實現的緩衝放大器以及90奈米CMOS製程的變壓器結合之功率放大器，最後是使用0.18微米CMOS和玻璃被動元件整合製程(GIPD)的電壓控制震盪器。 在此篇論文中，我們討論了放大器的一些基本概念，再提出了一個使用65奈米CMOS製程設計的73到84 GHz 緩衝放大器。我們使用了三級的共源極放大器而且使用被動元件來實現匹配網路。最後，整體的晶片面積分別是0.18 mm2 (包含pad)/0.127 mm2 (不含pad)。這顆放大器操作在1 V的偏壓，整體的電流大小為15 mA。這顆緩衝放大器在73到84 GHz之間提供了18.6±1dB的增益且於77 GHz下提供了18.6dB的增益且OP1dB為 -1 dBm。 接著，我們提出一個24 GHz的變壓器結合功率放大器。在提出如何設計這個放大器之前，我們先討論了功率放大器的偏壓選擇和不同的功率結合的方法。最後我們選擇了4路結合的變壓器當作輸出端的功率結合器。這個放大器使用了兩級的cascode架構。整體的晶片面積為0.92 mm2。此放大器在24 GHz下提供了14.1 dB的增益且OP1dB為21 dBm，而最大的輸出功率和最好的PAE分別為24.3 dBm以及7.7 %。 最後，我們提出了一個20.2 GHz的電壓控制震盪器。首先，我們先討論震盪器的基本概念和品質參數的定義。接著，兩種相位雜訊的模型也在此論文中被討論，藉由這兩種模型的解釋，可以對我們這次的設計有所幫助。我們使用0.18微米CMOS製程和GIPD製程來實現這個電路。此壓控震盪器的頻率可調範圍為30.8到33.8 GHz，在1 MHz偏移量下的相位雜訊則為-84.15 dBc/Hz。

Amplifiers and voltage-controlled oscillator play important roles in modern communication systems. We focus on the analysis and design of these two types of circuits in this thesis. Due to the advances of the process technology, the operation frequency of CMOS process is much higher than before. With the advantages of low cost and the ease of integration, many microwave and millimeter-wave circuits which used to be designed and fabricated by III-V technologies are now implemented in CMOS technology. This thesis presents three circuits: a buffer amplifier in 65-nm CMOS process and a transformer-combining power amplifier in 90-nm CMOS process, and a VCO implemented in 0.18-um CMOS process and GIPD is also included. In this thesis, we discuss the fundamentals of amplifiers. Then we implement a 73-to-84 GHz buffer amplifier in 65-nm CMOS process. The topology is a three-stage common-source amplifier and using lumped elements for matching networks. The total chip area of this amplifier is only 0.18 mm2/0.127 mm2 with pads/without pads. It is under 1 V supply and draws total current of 15 mA. The proposed buffer amplifier has the gain of 18.6±1 dB form 73 to 84 GHz and it provides the gain of 18.6 dB and OP1dB of -1 dBm at 77 GHz. Second, a 24-GHz transformer-combining power amplifier is presented. Before the amplifier design, we discuss about the bias selection of power amplifiers and different matching methodologies. Then we select a 4-way transformer as our output power combiner. The topology is a two-stage cascode circuit. The total chip area is 0.92 mm2. This amplifier provides the gain of 14.1 dB and the OP1dB is 21 dBm. Also, the maximum output power is 24.3 dBm and the maximum PAE is 7.7 % from the measurement results. Finally, a 20.2-GHz voltage-controlled oscillator (VCO) is presented. We discuss the fundamentals of oscillator and the definition of quality factor of first. Then, two models of the phase noise are introduced and are helpful to our design. We implement this VCO in 0.18-um CMOS process and GIPD process. The circuit demonstrates the tuning range from 30.8 to 33.8 GHz and the phase noise of -84.15 dBc/Hz at 1-MHz offset.