具變壓器回授電流重複使用之Q-band低雜訊放大器與低功耗ΔΣ分數型頻率合成器之設計與分析

Abstract

本篇論文，為克服互補式金氧半導體製程限制，提出了一系列創新的電路架構在對於CMOS毫米波電路及分數型頻率合成器做出相關之設計與分析。 在第二章中，低直流功率消耗、低雜訊之低雜訊放大器被提出且適用於可攜式之RF前端電路應用之上。藉由使用電流重複利用、以及基極偏壓等技術，使得此低雜訊放大器於毫米波的頻段之上能操作在減少的電源電壓之下且其直流功率消耗為微瓦等級，還能具有相當的小訊號增益。為了進一步地降低雜訊指數與偏壓電流，使用變壓器回授技術有利於在雜訊指數與輸入端匹配的取捨。在第三章中，低直流功率消耗分數型頻率合成器被提出且適用於無線通訊傳輸系統之上。藉由使用三角調變器型式架構的運用，於頻率合成器的頻寬之內，減緩了像是通道間距與分數突波、相位雜訊所衍生出的問題。在第四章中，利用突波抑制技術基於波型的亂數化與疊接式除頻器等技巧使得整體鎖相迴路的突波能量強度降低與具較低的直流功率消耗。在第五章中，透過採用串聯電感補償與變壓器回授等技術使得除二頻率除頻器的鎖定頻寬能有效增大。

To alleviate the limitations imposed on CMOS technique, some design techniques are developed for CMOS millimeter-wave integrated circuits and fractional-N frequency synthesizer in this thesis. In chapter 2, an ultra-low-power and low-noise amplifier is presented for CMOS RF frontends. By employing current-reused, and forward-body-bias techniques, a low-noise amplifier can operate at a reduced supply voltage with micro-watt dc power consumption while maintaining reasonable gain performance at millimeter-wave frequencies. To reduce noise factor and bias current simultaneously, transformer feedback technique is selected to make compromise between noise figure and input matching. In chapter 3, a low-power fractional-N frequency synthesizer is presented for wireless communication system. By employing Δ-Σ modulator-based topology, problems caused by narrow channel spacing, fractional spurs and noises are alleviated within the synthesizer bandwidth. In chapter 4, a spur suppression technique based on the randomization of pulse position and cascoded divider architecture are adopted to reduce reference spur and lower dc power consumption. In chapter 5, by adopting a series-peaking and transformer-feedback techniques, the locking range of the injection-locked frequency divider is effectively enhanced.