Please use this identifier to cite or link to this item:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/16096Full metadata record
| ???org.dspace.app.webui.jsptag.ItemTag.dcfield??? | Value | Language |
|---|---|---|
| dc.contributor.advisor | 黃天偉 | |
| dc.contributor.author | Min Huang | en |
| dc.contributor.author | 黃敏 | zh_TW |
| dc.date.accessioned | 2021-06-07T18:00:54Z | - |
| dc.date.copyright | 2012-08-15 | |
| dc.date.issued | 2012 | |
| dc.date.submitted | 2012-08-06 | |
| dc.identifier.citation | [1] E. Cohen, S. Ravid, and D. Ritter, “An ultra low power LNA with 15dB gain and 4.4dB NF in 90nm CMOS process for 60 GHz phase array radio,” in IEEE Radio Frequency Integrated Circuits Symposium Digest, June 2008, pp. 61–64.
[2] W.-H. Lin, J.-H. Tsai, Y.-N. Jen, T.-W. Huang, and H. Wang, “A 0.7-V 60-GHz low-power LNA with forward body bias technique in 90 nm CMOS process,” in 2009 European Microwave Integrated Circuits Conference Digest, pp. 393-396, Rome, Italy, September 2009. [3] B.-J. Huang, K.-Y. Lin, and H. Wang, “Millimeter-wave low power and miniature CMOS multi-cascode low noise amplifiers with noise reduction topology,” IEEE Transactions on Microwave Theory and Techniques, vol. 57, no. 12, pp. 3049-3059, December 2009. [4] H.-C. Yeh, H. Wang, “A Miniature Q-band CMOS LNA with Quadruple-Cascode Topology,” in IEEE MTT-S International Microwave Symposium Digest, June 2011. [5] J.-H. Tsai, W.-C. Chen, T.-P. Wang, T.-W. Huang, and H. Wang, “A miniature Q-band low noise amplifier using 0.13-μm CMOS technology.” IEEE Microwave and Wireless Components Letters, vol. 16, no. 6, pp. 327–329, June 2006. [6] M. Varonnen, M. Karkkainen, M. Kantanen, and K. A. I. Halonen, “Millimeter-wave integrated circuits in 65-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 43, no. 9, pp. 1991–2002, September 2008. [7] K. Nishikawa, T. Enoki, S. Sugitani, and I. Toyoda, “0.4 V, 5.6 mW InP HEMT V-band Low-Noise Amplifier MMIC,” in IEEE MTT-S International Microwave Symposium Digest, June 2006, pp. 810–813. [8] X. Li, S. Shekhar and D. J. Allstot, “Gm-boosted common-gate LNA and differential colpitts VCO/QVCO in 0.18μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2609-2619, December 2005. [9] D. Wu, R. Huang, W. Wong, and Y. Wang, “A 0.4-V low noise amplifier using forward body bias technology for 5 GHz application,” IEEE Microwave and Wireless Components Letters vol. 17, no. 7, pp. 543-545, July 2007. [10] H.-H. Hsieh and L.-H. Lu, “Design of ultra-low-voltage RF frontends with complementary current-reused architectures,” IEEE Transactions on Microwave Theory and Techniques, vol. 55, no. 7, pp. 1445-1458, July 2007. [11] P. Andreani, and H. Sjoland , “Noise Optimization of an Inductively Degenerated CMOS Low Noise Amplifier,” IEEE Transactions on Circuits and Systems- II: Analog and Digital Signal Processing, vol. 48, pp. 835–841, September 2001. [12] J. J. Zhou, and D. J. Allstot, “Monolithic Transformers and Their Application in a Differential CMOS RF Low-Noise Amplifier,” IEEE Journal of Solid-State Circuits, vol. 33, no. 12, pp. 2020–2027, December 1998. [13] D. J. Cassan, and J. R. Long, “A 1-V Transformer-Feedback Low-Noise Amplifier for 5-GHz Wireless LAN in 0.18-μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 38, no. 3, pp. 427–435, March 2003. [14] J. R. Long, “Monolithic Transformers for Silicon RF IC Design,” IEEE Journal of Solid-State Circuits, vol. 35, no. 9, pp. 1368–1382, September 2000. [15] T. Riley, M. Copeland, and T. Kwasniewski, “Delta-Sigma Modulation in Fractional-N Frequency Synthesis,” IEEE Journal of Solid-State Circuits, vol. 28, no. 5, pp. 553–559, May 1993. [16] T. P. Kenny, T. A. D. Riley, N. M. Filiol, and M. A. Copeland, “Design and realization of a digital Δ-Σ modulator for fractional-N frequency synthesis,” IEEE Transactions on Vehicular Technology, vol. 48, no. 2, pp.510–521, March 1999. [17] M. H. Perrot, M. D. Trott, and C. G. Sodini, “A modeling approach for Σ-Δ fractional-N frequency synthesizer allowing straightforward noise analysis,” IEEE Journal of Solid-State Circuits, vol. 37, no. 8, pp.835–844, August 2002. [18] S. Laventino, C. Samori, A. Bonfanti, A. Lacaita, and V. Boccuzzi, “Frequency dependence on bias current in 5 GHz CMOS VCOs: Impact on tuning range and flicker noise upconversion,” IEEE Journal of Solid-State Circuits, vol. 37, no. 8, pp. 1003-1011, August 2002. [19] W.-H. Chiu, T.-S. Chang, and T.-H. Lin, 'A Charge Pump Current Calibration Technique for DS Fractional-N PLLs in 0.18-μm CMOS,' in IEEE Asian Solid-State Circuits Conference, pp. 73-76, November 2009. [20] C.-L. Ti, Y.-H. Liu, and T.-H. Lin, “A 2.4-GHz Fractional-N PLL with a PFD/CP Linearization and an Improved CP Circuit,” in IEEE International Symposium on Circuits and Systems, pp. 1728-1731, May 2008. [21] H. Hedayati and B. Bakkaloglu, “A 3GHz Wideband ΣΔ Fractional-N Synthesizer with Voltage-Mode Exponential CP-PFD,” in IEEE Radio Frequency Integrated Circuits Symposium Digest, pp. 325-328, June 2009. [22] H.-Y. Jian, Z. Xu, Y.-C. Wu, M.-C. Frank Chang, 'A Fractional-N PLL for Multiband (0.8-6GHz) Communications Using Binary-Weighted D/A Differentiator and Offset-Frequency delta-sigma Modulator', IEEE Journal of Solid-State Circuits, vol.45, no.4, pp.768-780, April 2010. [23] S. E. Meninger and M. H. Perrott, “A 1-MHz bandwidth 3.6-GHz 0.18-μm CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise,” IEEE Journal of Solid-State Circuits, vol. 41, no. 4, pp. 966–980, April 2006. [24] T.-C. Chueh, W.-H. Chen, and D.-R. Huang, “A 0.13μm CMOS ΔΣ Fractional-N Synthesizer for WiMAX Application,” in 2009 European Microwave Integrated Circuits Conference Digest, pp. 262-265, Rome, Italy, September 2009. [25] H. Hedayati, W. Khalil and B. Bakkaloglu, “A 1 MHz Bandwidth, 6 GHz 0.18μm CMOS Type-I ΔΣ Fractional-N Synthesizer for WiMAX Applications,” IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3244–3252, December 2009. [26] C.-F. Liang, H.-H. Chen, and S.-I. Liu, “Spur-suppression techniques for frequency synthesizers,” IEEE Transactions Circuits and Systems- II: Express Briefs, vol. 54, pp. 653-657, August 2007. [27] Y. S. Choi, D. H. Han “Gain-boosting charge pump for current mismatch in phase-locked loops”, IEEE Transactions Circuits and Systems- II: Express Briefs, vol. 53, No. 10, pp. 1022–1025, October 2006. [28] K. Kwok and H. C. Luong, “Ultra-low-voltage high-performance CMOS VCOs using transformer feedback,” IEEE Journal of Solid-State Circuits, vol. 40, no. 3, pp. 652–660, March 2005. [29] D. B. Leeson, “A simple model of feedback oscillator noise spectrum,” IEEE Proceedings, vol. 54, no. 2, pp. 329–330, February 1966. [30] J. Yang, C.-Y. Kim, D.-W. Kim, and S. Hong, “Design of a 24-GHz CMOS VCO With an Asymmetric-Width Transformer,” IEEE Transactions Circuits and Systems-II: Analog and Digital Signal Processing, vol. 57, pp. 173-177, March 2010. [31] B. Razavi, “A study of injection locking and pulling in oscillators,” IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1415-1424, September 2004. [32] H. R. Rategh and T. H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE Journal of Solid-State Circuits, vol. 34, no. 6, pp. 813-821, June 1999. [33] C.-Y. Wu and C.-Y. Yu, “Design and analysis of a millimeter-wave direct injection-locked frequency divider with large frequency locking range,” IEEE Transactions on Microwave Theory and Techniques, vol. 55, no. 8, pp. 1649-1658, August 2007. [34] A. W. L. Ng, G. C. T. Leung, K.-C. Kwok, L. L. K. Leung, and H.C. Luong, “A 1-V 24-GHz 17.5-mW phase-locked loop in a 0.18-μm CMOS process,” IEEE Journal of Solid-State Circuits, vol. 41, no. 6, pp.1236–1244, June 2006. [35] Y. Ding and K. K. O, “A 21-GHz 8-Modulus Prescaler and a 20-GHz Phase-Locked Loop Fabricated in 130-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 42, no. 6, pp.1240–1249, June 2007. [36] O. Richard, A. Siligaris, F. Badets, C. Dehos, C. Dufis, P. Busson, P. Vincent, D. Belot, and P. Urard, “A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for Wireless HD Applications,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, February 2010, pp. 252-253. [37] J. Kim, J. K. Kim, B. J. Lee, N. Kim, D. K. Jeong, and W. Kim,“A 20-GHz phase-locked loop for 40-Gb/s serializing transmitter in 0.13-um CMOS,” IEEE Journal of Solid-State Circuits, vol. 41, no. 4, pp.899–908, April 2006. [38] Y.-H. Lin, J.-H. Tsai, Y.-H. Kuo, and T.-W. Huang, “An Ultra Low-Power 24 GHz Phase-Lock-Loop with Low Phase-Noise VCO Embedded in 0.18μm CMOS Process,” Proceedings of the Asia-Pacific Microwave Conference 2011. [39] B. Razavi, K. F. Lee, and R.-H. Yan, “A 13.4-GHz CMOS frequency divider,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, February 1994, pp. 176-177. [40] H. Wang, “A 1.8 V 3 mW 16.8 GHz frequency divider in 0.25 μm CMOS,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, February 2000, pp. 196-197. [41] S. Verma, H. R. Rategh, and T. H. Lee, “A unified model for injection-locked frequency dividers,” IEEE Journal of Solid-State Circuits, vol. 38, no. 6, pp. 1015-1027, June 2003. [42] H.-H. Hsieh, H.-S. Chen and L.-H. Lu, “A V-Band divide-by-four direct injection-locked frequency divider in 0.18-mm CMOS,” IEEE Transactions on Microwave Theory and Techniques, vol. 59, no. 2, pp. 393-405, February 2011. [43] J.-C. Chien and L.-H. Lu, “40GHz wide-locking-range regenerative frequency divider and low-phase-noise balanced VCO in 0.18mm CMOS,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, February 2007, pp. 544-545. [44] T.-N. Luo and Y.-J. E. Chen, “A 0.8-mW 55-GHz dual-injection locked CMOS frequency divider,” IEEE Transactions on Microwave Theory and Techniques, vol. 56, no. 3, pp. 620–625, March 2008. [45] C. Shen and H. C. Luong, “A 0.55-V 25-GHz Transformer-Coupled Frequency Divider with Quadrature Outputs,” in IEEE Asian Solid-State Circuits Conference, pp. 324-327, November 2007. [46] T. Shibasaki, H. Tamura, K. Kanda, H. Yamaguchi, J. Ogawa and T. Kuroda, “20-GHz quadrature injection-locked LC dividers with enhanced locking range,” IEEE Journal of Solid-State Circuits, vol. 43, no. 3, pp. 610-618, March 2008. [47] Z.-D. Huang, C.-Y. Wu and B.-C. Huang, “Design of 24-GHz 0.8-V 1.51-mW coupling current-mode injection-locked frequency divider with wide locking range,” IEEE Transactions on Microwave Theory and Techniques, vol. 57, no. 8, pp. 1948–1958, August 2009. [48] Y.-H. Kuo, J.-H. Tsai, and T.-W. Huang, “A 1.5-mW, 23.6% Frequency Locking Range, 24-GHz Injection-Locked Frequency Divider,” in 2010 European Microwave Integrated Circuits Conference Digest, pp. 73-76, Paris, France, September 2010. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/16096 | - |
| dc.description.abstract | 本篇論文，為克服互補式金氧半導體製程限制，提出了一系列創新的電路架構在對於CMOS毫米波電路及分數型頻率合成器做出相關之設計與分析。
在第二章中，低直流功率消耗、低雜訊之低雜訊放大器被提出且適用於可攜式之RF前端電路應用之上。藉由使用電流重複利用、以及基極偏壓等技術，使得此低雜訊放大器於毫米波的頻段之上能操作在減少的電源電壓之下且其直流功率消耗為微瓦等級，還能具有相當的小訊號增益。為了進一步地降低雜訊指數與偏壓電流，使用變壓器回授技術有利於在雜訊指數與輸入端匹配的取捨。在第三章中，低直流功率消耗分數型頻率合成器被提出且適用於無線通訊傳輸系統之上。藉由使用三角調變器型式架構的運用，於頻率合成器的頻寬之內，減緩了像是通道間距與分數突波、相位雜訊所衍生出的問題。在第四章中，利用突波抑制技術基於波型的亂數化與疊接式除頻器等技巧使得整體鎖相迴路的突波能量強度降低與具較低的直流功率消耗。在第五章中，透過採用串聯電感補償與變壓器回授等技術使得除二頻率除頻器的鎖定頻寬能有效增大。 | zh_TW |
| dc.description.abstract | To alleviate the limitations imposed on CMOS technique, some design techniques are developed for CMOS millimeter-wave integrated circuits and fractional-N frequency synthesizer in this thesis.
In chapter 2, an ultra-low-power and low-noise amplifier is presented for CMOS RF frontends. By employing current-reused, and forward-body-bias techniques, a low-noise amplifier can operate at a reduced supply voltage with micro-watt dc power consumption while maintaining reasonable gain performance at millimeter-wave frequencies. To reduce noise factor and bias current simultaneously, transformer feedback technique is selected to make compromise between noise figure and input matching. In chapter 3, a low-power fractional-N frequency synthesizer is presented for wireless communication system. By employing Δ-Σ modulator-based topology, problems caused by narrow channel spacing, fractional spurs and noises are alleviated within the synthesizer bandwidth. In chapter 4, a spur suppression technique based on the randomization of pulse position and cascoded divider architecture are adopted to reduce reference spur and lower dc power consumption. In chapter 5, by adopting a series-peaking and transformer-feedback techniques, the locking range of the injection-locked frequency divider is effectively enhanced. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-07T18:00:54Z (GMT). No. of bitstreams: 1 ntu-101-R99942023-1.pdf: 9444634 bytes, checksum: 7b507a76e5012a39bc78d2554fcf7fe7 (MD5) Previous issue date: 2012 | en |
| dc.description.tableofcontents | CONTENTS
口試委員會審定書 # 誌謝 i 中文摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES viii LIST OF TABLES xvi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 A 917-μW Q-band Transformer-Feedback Current-Reused Low Noise Amplifier Using 90-nm CMOS Technology 3 2.1 Low Noise Amplifier Design Topologies 4 2.1.1 Common-Source Topology 4 2.1.2 Common-Gate Topology 8 2.1.3 Comparisons of Common-Source and Common-Gate Topologies 11 2.2 Gm-boosted Common-Gate Topology 12 2.2.1 Reasonable Implementation 13 2.3 Low Power Techniques 19 2.3.1 Current-Reused Technique 19 2.3.2 Forward-Body-Bias Technique 22 2.4 Proposed Circuit Topology 25 2.4.1 Device Size and Gate Bias 26 2.4.2 Spiral Transformer 27 2.4.3 Small-Signal Characteristics 28 2.5 Circuit Implementation 29 2.6 Experimental results 30 2.7 Summary 36 Chapter 3 A Low Power 4.8GHz~6.2GHz 3-bits ΔΣ Fractional-N Frequency Synthesizer 38 3.1 Digital ΔΣ Modulator 38 3.1.1 Digital Phase Accumulator (DPA) 39 3.1.2 First-Order ΔΣ Modulator 40 3.1.3 Multi-Stage-Noise-Shaping (MASH) ΔΣ Modulators 41 3.1.4 Quantization Noise 42 3.2 The Implementation and Simulation of ΔΣ Modulator 43 3.3 Proposed Architecture 50 3.3.1 Phase Frequency Detector (PFD) 51 3.3.2 Charge Pump (CP) 52 3.3.3 Loop Filter (LF) 52 3.3.4 Voltage Controlled Oscillator (VCO) 53 3.3.5 Divider Chain (DIV) 56 3.3.6 Transistor-Level Simulation 59 3.4 Experimental Results 62 3.5 Summary 68 Chapter 4 A Spur-Suppression Phase-Lock-Loop for 24GHz ISM-Band Application 69 4.1 Reference Spur 69 4.2 Proposed Architecture 70 4.2.1 Phase Lock Loop Architecture 71 4.2.2 Spur Suppression Technique 72 4.3 Building Blocks and Transistor-Level Simulation 75 4.3.1 Lock Detector (LD) 76 4.3.2 Pseudo Random Binary Sequence (PRBS) 77 4.3.3 Phase Frequency Detector (PFD) 79 4.3.4 Charge Pump (CP) 80 4.3.5 Loop Filter (LF) 82 4.3.6 Voltage Controlled Oscillator (VCO) 83 4.3.7 Divider Chain (DIV) 90 4.3.8 Transistor-Level Simulation 97 4.4 Experimental Results 102 4.5 Summary 114 Chapter 5 A K-band Transformer-Feedback Injection-Locked Frequency Divider 115 5.1 Operation Principles of divide-by-two ILFD 116 5.1.1 Modeling 116 5.1.2 Free-Running Oscillation 117 5.1.3 Frequency Division 117 5.2 Proposed Circuit Topology 121 5.2.1 Input Locking Range 122 5.2.2 Phase Noise 125 5.2.3 Design Parameters 126 5.3 Circuit Implementation 127 5.4 Experimental Results 129 5.5 Summary 134 Chapter 6 Conclusions 135 REFERENCE 137 PUBLICATIONS 144 | |
| dc.language.iso | en | |
| dc.title | 具變壓器回授電流重複使用之Q-band低雜訊放大器與低功耗ΔΣ分數型頻率合成器之設計與分析 | zh_TW |
| dc.title | Design and Analysis of Q-band Transformer-Feedback Current-Reused LNA and Low Power ΔΣ Fractional-N Frequency Synthesizer | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 100-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 薛光華,張鴻埜,蔡政翰 | |
| dc.subject.keyword | 低雜訊放大器,分數型頻率合成器,鎖相迴路,注入鎖定除頻器, | zh_TW |
| dc.subject.keyword | Low-noise amplifier (LNA),fractional-N frequency synthesizer,phase-locked loop (PLL),injection-locked frequency divider (ILFD), | en |
| dc.relation.page | 144 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2012-08-07 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| Appears in Collections: | 電信工程學研究所 | |
Files in This Item:
| File | Size | Format | |
|---|---|---|---|
| ntu-101-1.pdf Restricted Access | 9.22 MB | Adobe PDF |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.