矽金氧半電晶體與接觸電阻的變溫特性

Abstract

隨著平面電晶體元件尺寸縮放逼近物理極限，量子穿隧效應使閘極漏電劇增，摩爾定律的延續除了走向元件結構及材料的創新，範式的轉移也是增加算力非常具前瞻性的策略。大規模量子計算架構開始由實驗室轉向商業化應用，開發能在極低溫環境下直接封裝於量子處理器旁的低溫電晶體（Cryo-CMOS）控制電路，已成為降低訊號延遲與解決熱負載瓶頸的關鍵要素。傳統互補式場效電晶體（CMOS）設計在極低溫下會遭遇顯著的物理性質偏差，針對各項參數提出基於物理的精簡模型將是成功設計低溫元件的基礎。因此本論文將著重在矽電晶體與接觸電阻元件的變溫特性，以幫助了解其低溫行為。 第二章彙整了近年對於半導體物理以及電晶體電性的低溫特性的發現，如載子凍結效應、臨界電壓飄移、次臨界擺幅飽和等現象，以及其可能的物理模型解釋。接著詳細記錄自行製作矽基電晶體的製作流程，並進行量測與分析。n型電晶體與p型電晶體在低溫皆出現臨界電壓上升與次臨界擺幅下降的趨勢，其中n型電晶體的結果觀察到在約50 K時飽和的現象，可用能帶尾態模型來解釋。電晶體效能表現的部分上，n型電晶體導通電流隨溫度下降而上升，同時聲子散射在低溫的下降也使電子遷移率出現3倍於室溫值的提升；p型電晶體卻顯示出相反的趨勢，顯示n型電晶體相對p型電晶體具有良好的介面品質與接觸電阻率，加上電洞較大的有效質量，使得p型電晶體的轉導與載子遷移率在低溫劣化。 第三章深入研究了接觸電阻的變溫特性。首先介紹金屬-半導體介面的基礎特性及量測方法，並整理不同文獻中優化室溫與低溫電阻率的可行方案，最後詳細描述RTLM量測架構的製作過程，並對鎳矽與鎳鍺介面的變溫量測及分析。鎳/n型矽與鎳/p型矽元件在低溫皆出現劣化的狀況，即使其較高的矽基板摻雜濃度，傳輸特性表現仍無法達到場發射（FE）模式，兩者分別呈現了熱場發射（TFE）與熱發射（TE）特徵，兩者在低溫都會因熱能被嚴重壓制而使接觸電阻率指數性飆升。而鎳/n型鍺元件雖具有相似溫度趨勢，但整體熱穩定度較高，從室溫到低溫始終維持在同一量級。

With large-scale quantum computers transition from laboratories to commercialization, the development of cryogenic CMOS (Cryo-CMOS) control circuits is critical for minimizing signal latency and overcoming thermal load constraints. However, conventional CMOS designs encounter significant physical deviations at cryogenic temperatures from room temperature. Establishing physics-based compact models is therefore essential for the successful design of cryogenic devices. Therefore, this thesis focuses on characteristic of Si MOSFETs and contact resistance under different temperatures for better understanding of their cryogenic behavior. Chapter 2 introduces recent findings on cryogenic semiconductor physics and transistor electrical characteristics, including carrier freeze-out, threshold voltage shift, and subthreshold swing saturation, along with their underlying physical mechanisms. The fabrication process of silicon-based transistors is detailed, followed by comprehensive analysis and characterization. Both n-type and p-type transistors exhibit increased threshold voltage and reduced subthreshold swing at low temperatures. Notably, SS saturation in the n-type transistors occurs at approximately 50 K. Regarding device performance, the ON-current of n-type transistors improves as the temperature decreases due to reduced phonon scattering at low temperatures to enhances electron mobility. Conversely, p-type transistors show an opposing trend, which might be due to inferior interface quality and larger carrier effective mass. Chapter 3 investigates the temperature-dependent characteristics of contact resistance using a Refined Transmission Line Method (RTLM) structure. Analysis of Ni/Si and Ni/Ge interfaces reveals that Ni/n-Si and Ni/p-Si interfaces degrade at low temperatures. Despite high substrate doping levels, their transport characteristics fail to reach the Field Emission (FE) mode, instead exhibiting Thermionic Field Emission (TFE) and Thermionic Emission (TE) behavior. The suppressed thermal energy at low temperatures causes contact resistivity to increase exponentially. While Ni/n-Ge devices follow a similar trend, they demonstrate superior thermal stability, maintaining resistivity within the same order of magnitude from room temperature down to cryogenic levels.