請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/102325完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李峻霣 | zh_TW |
| dc.contributor.advisor | Jiun-Yun Li | en |
| dc.contributor.author | 謝菩家 | zh_TW |
| dc.contributor.author | Pu-Jia Hsieh | en |
| dc.date.accessioned | 2026-06-02T03:48:16Z | - |
| dc.date.available | 2026-06-02 | - |
| dc.date.copyright | 2026-05-28 | - |
| dc.date.issued | 2026 | - |
| dc.date.submitted | 2026-05-12 | - |
| dc.identifier.citation | [1] C. A. Mack, "Fifty years of Moore's law," IEEE Trans. Semicond. Manuf., vol. 24, no. 2, pp. 202–207, 2011.
[2] "Supercomputer Power," Our World in Data. [Online]. Available: https://ourworldindata.org/grapher/supercomputer-power-flops. [Accessed: Apr. 1, 2026]. [3] T. N. Theis and H.-S. P. Wong, "The end of Moore's law: A new beginning for information technology," Comput. Sci. Eng., vol. 19, no. 2, pp. 41–50, 2017. [4] D. Nagy et al., "FinFET versus gate-all-around nanowire FET: performance, scaling, and variability," IEEE J. Electron Devices Soc., vol. 6, pp. 332–340, 2018. [5] A. Steane, "Quantum computing," Rep. Prog. Phys., vol. 61, no. 2, pp. 117–173, 1998. [6] E. Charbon et al., "Cryo-CMOS for quantum computing," in Proc. IEEE Int. Electron Devices Meeting (IEDM), 2016, pp. 13.5.1–13.5.4. [7] F. Sebastiano et al., "Cryo-CMOS electronic control for scalable quantum computing," in Proc. 54th Annu. Design Autom. Conf. (DAC), Art. no. 71, pp. 1-6, 2017 [8] F. A. Zwanenburg et al., "Silicon quantum electronics," Rev. Mod. Phys., vol. 85, no. 3, pp. 961–1019, 2013. [9] M. F. Gonzalez-Zalba et al., "Scaling silicon-based quantum computing using CMOS technology," Nat. Electron., vol. 4, no. 12, pp. 872–884, 2021. [10] B. Patra et al., "Cryo-CMOS circuits and systems for quantum computing applications," IEEE J. Solid-State Circuits, vol. 53, no. 1, pp. 309–321, 2017. [11] S. M. Sze, Y. Li, and K. K. Ng, Physics of Semiconductor Devices. Hoboken, NJ, USA: John Wiley & Sons, 2021. [12] A. Beckers, F. Jazaeri, and C. Enz, "Cryogenic MOS transistor model," IEEE Trans. Electron Devices, vol. 65, no. 9, pp. 3617–3625, 2018. [13] A. K. Jonscher, "Semiconductors at cryogenic temperatures," Proc. IEEE, vol. 52, no. 10, pp. 1092–1104, 1964. [14] K. P. O’Donnell and X. Chen, "Temperature dependence of semiconductor band gaps," Appl. Phys. Lett., vol. 58, no. 25, pp. 2924–2926, 1991. [15] P. Geng et al., "A novel theoretical model for the temperature dependence of band gap energy in semiconductors," J. Phys. D, Appl. Phys., vol. 50, no. 40, p. 40LT02, 2017. [16] W. Manzoor, A. K. Dutta, and Y. S. Chauhan, "Analytical approximation of surface potential and analysis of C–V characteristics of bulk MOSFETs at cryogenic temperatures," Microelectronics J., vol. 129, p. 105586, 2022. [17] A. Pirovano et al., "Novel low-temperature CV technique for MOS doping profile determination near the Si/SiO2 interface," IEEE Trans. Electron Devices, vol. 48, no. 4, pp. 750–757, 2002. [18] P. Bouillon and T. Skotnicki, "Theoretical analysis of kink effect in CV characteristics of indium-implanted NMOS capacitors," IEEE Electron Device Lett., vol. 19, no. 1, pp. 19–22, 2002. [19] R. Divakaruni, "MOS investigations in the freezeout regime," Ph.D. dissertation, Univ. California, Los Angeles, CA, USA, 1994. [20] C. R. Viswanathan, R. Divakaruni, and J. Kizziar, "Low-temperature CV dispersion in MOS devices," IEEE Electron Device Lett., vol. 12, no. 9, pp. 503–505, 2002. [21] S. Gupta et al., "Investigation and modeling of multifrequency CV characteristics for 10-nm bulk FinFETs at cryogenic temperatures," Solid-State Electron., vol. 211, p. 108820, 2024. [22] M. Cassé et al., "FDSOI for cryoCMOS electronics: device characterization towards compact model," in Proc. IEEE Int. Electron Devices Meeting (IEDM), 2022, pp. 543–546. [23] H. Oka et al., "Effect of conduction band edge states on coulomb-limiting electron mobility in cryogenic MOSFET operation," in Proc. IEEE Symp. VLSI Technol. Circuits, 2022, pp. 248–249. [24] W. Manzoor, A. K. Dutta, and Y. S. Chauhan, "A comprehensive study of threshold voltage extraction techniques from room to cryogenic temperatures," IEEE J. Electron Devices Soc., 2024, doi: 10.1109/JEDS. 2024, 13: 915-923. [25] A. Beckers, "Cryogenic MOSFET modeling for large-scale quantum computing," Ph.D. dissertation, École Polytechnique Fédérale de Lausanne, Lausanne, Switzerland, 2021. [26] A. Beckers et al., "Physical model of low-temperature to cryogenic threshold voltage in MOSFETs," IEEE J. Electron Devices Soc., vol. 8, pp. 780–788, 2020. [27] H. Hanamura et al., "Operation of bulk CMOS devices at very low temperatures," IEEE J. Solid-State Circuits, vol. 21, no. 3, pp. 484–490, 1986. [28] H.-C. Han et al., "Novel approach to FDSOI threshold voltage model validated at cryogenic temperatures," IEEE Access, vol. 11, pp. 56951–56957, 2023. [29] M. Cassé and G. Ghibaudo, "FDSOI transistors for cryo CMOS applications," in Low-Temperature Technologies and Applications, 2022, p. 17. [30] G. Ghibaudo et al., "On the modelling of temperature dependence of subthreshold swing in MOSFETs down to cryogenic temperature," Solid-State Electron., vol. 170, p. 107820, 2020. [31] A. Beckers, F. Jazaeri, and C. Enz, "Theoretical limit of low temperature subthreshold swing in field-effect transistors," IEEE Electron Device Lett., vol. 41, no. 2, pp. 276–279, 2019. [32] H. Bohuslavskyi et al., "Cryogenic subthreshold swing saturation in FD-SOI MOSFETs described with band broadening," IEEE Electron Device Lett., vol. 40, no. 5, pp. 784–787, 2019. [33] R. M. Incandela et al., "Characterization and compact modeling of nanometer CMOS transistors at deep-cryogenic temperatures," IEEE J. Electron Devices Soc., vol. 6, pp. 996–1006, 2018. [34] P. Galy et al., "Cryogenic temperature characterization of a 28-nm FD-SOI dedicated structure for advanced CMOS and quantum technologies co-integration," IEEE J. Electron Devices Soc., vol. 6, pp. 594–600, 2018. [35] K. Triantopoulos et al., "Self-heating effect in FDSOI transistors down to cryogenic operation at 4.2 K," IEEE Trans. Electron Devices, vol. 66, no. 8, pp. 3498–3505, 2019. [36] A. Beckers, F. Jazaeri, and C. Enz, "Inflection phenomenon in cryogenic MOSFET behavior," IEEE Trans. Electron Devices, vol. 67, no. 3, pp. 1357–1360, 2020. [37] X. Zhang et al., "Modeling of the subthreshold swing in cryogenic MOSFET with the combination of Gaussian band tail and Gaussian interface state," IEEE Trans. Electron Devices, vol. 71, no. 2, pp. 1173–1178, 2023. [38] M.-S. Kang et al., "Characterization and quantitative understanding of subthreshold swing of Si metal–oxide–semiconductor field effect transistors at cryogenic temperatures," J. Appl. Phys., vol. 136, no. 19, 2024. [39] M.-S. Kang et al., "Influence of substrate impurity concentration on sub-threshold swing of Si n-channel MOSFETs at cryogenic temperatures down to 4 K," Jpn. J. Appl. Phys., vol. 62, p. SC1062, 2023. [40] J. Lee et al., "Subthreshold swing (SS) degradation as the origin of SS saturation in nanoscale cryogenic gate-all-around MOSFETs," Semicond. Sci. Technol., vol. 40, no. 9, p. 095002, 2025. [41] E. H. Nicollian and J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology. Hoboken, NJ, USA: John Wiley & Sons, 2002. [42] T.-Y. Yang et al., "Quantum transport in 40-nm MOSFETs at deep-cryogenic temperatures," IEEE Electron Device Lett., vol. 41, no. 7, pp. 981–984, 2020. [43] S. Sekiguchi et al., "Subthreshold swing in silicon gate-all-around nanowire and fully depleted SOI MOSFETs at cryogenic temperature," IEEE J. Electron Devices Soc., vol. 9, pp. 1151–1154, 2021. [44] H. Oka et al., "Origin of low-frequency noise in Si n-MOSFET at cryogenic temperatures: The effect of interface quality," IEEE Access, vol. 11, pp. 121567–121573, 2023. [45] J. Tao et al., "Extrinsic and intrinsic frequency dispersion of high-k materials in capacitance-voltage measurements," Materials, vol. 5, no. 6, pp. 1005–1032, 2012. [46] D. K. Schroder, Semiconductor Material and Device Characterization, 3rd ed. Hoboken, NJ, USA: John Wiley & Sons, 2015. [47] A. Scorzoni and M. Finetti, "Metal/semiconductor contact resistivity and its determination from contact resistance measurements," Mater. Sci. Rep., vol. 3, no. 2, pp. 79–137, 1988. [48] R. Dormaier and S. E. Mohney, "Factors controlling the resistance of Ohmic contacts to n-InGaAs," J. Vac. Sci. Technol. B, vol. 30, no. 3, 2012. [49] R. Saligram, S. Datta, and A. Raychowdhury, "Design space exploration of interconnect materials for cryogenic operation: Electrical and thermal analyses," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 69, no. 11, pp. 4610–4618, 2022. [50] J. Robertson and L. Lin, "Fermi level pinning in Si, Ge and GaAs systems-MIGS or defects?," in Proc. IEEE Int. Electron Devices Meeting (IEDM), pp. 1-4, 2009. [51] L. Lin, Y. Guo, and J. Robertson, "Metal silicide Schottky barriers on Si and Ge show weaker Fermi level pinning," Appl. Phys. Lett., vol. 101, no. 5, 2012. [52] X. Liu et al., "Fermi level pinning dependent 2D semiconductor devices: challenges and prospects," Adv. Mater., vol. 34, no. 15, p. 2108425, 2022. [53] S.-H. Kim et al., "Fermi-level unpinning using a Ge-passivated metal–interlayer–semiconductor structure for non-alloyed ohmic contact of high-electron-mobility transistors," IEEE Electron Device Lett., vol. 36, no. 9, pp. 884–886, 2015. [54] M. Yuan et al., "Charge redistribution to reduce contact resistivity in NiSi/Si system through interface modification: A first-principles study," Appl. Phys. Lett., vol. 126, no. 13, 2025. [55] E. H. Rhoderick, "Metal-semiconductor contacts," IEE Proc. I (Solid-State Electron. Devices), vol. 129, no. 1, pp. 1–14, 1982. [56] N. Duan et al., "A modified scheme to reduce the specific contact resistivity of NiSi/Si contacts by means of dopant segregation technique," ECS J. Solid State Sci. Technol., vol. 6, no. 12, p. P904, 2017. [57] C. C. Han et al., "The temperature dependence of the contact resistivity of the Si/Ni (Mg) nonspiking contact scheme on p‐GaAs," J. Appl. Phys., vol. 69, no. 5, pp. 3124–3129, 1991. [58] D. Gunnarsson et al., "Interfacial engineering of semiconductor–superconductor junctions for high performance micro-coolers," Sci. Rep., vol. 5, no. 1, p. 17398, 2015. [59] C. B. Beauchamp et al., "Superconductivity in AuNiGe ohmic contacts to a GaAs-based high mobility two-dimensional electron gas," Appl. Phys. Lett., vol. 117, no. 16, 2020. [60] C. M. Polley, W. R. Clarke, and M. Y. Simmons, "Comparison of nickel silicide and aluminium ohmic contact metallizations for low-temperature quantum transport measurements," Nanoscale Res. Lett., vol. 6, no. 1, p. 538, 2011. [61] J. Talvacchio, "Electrical contact to superconductors," IEEE Trans. Comp., Hybrids, Manuf. Technol., vol. 12, no. 1, pp. 21–31, 2002. [62] P. Nash and A. Nash, "The Ni−Si (nickel-silicon) system," Bull. Alloy Phase Diagrams, vol. 8, no. 1, pp. 6–14, 1987. [63] K. Tsutsui et al., "Analysis of irregular increase in sheet resistance of Ni silicides on transition from NiSi to NiSi$_2$," Microelectron. Eng., vol. 85, no. 2, pp. 315–319, 2008. [64] A. Nash and P. Nash, "The Ge−Ni (germanium-nickel) system," Bull. Alloy Phase Diagrams, vol. 8, no. 3, pp. 255–264, 1987. [65] R. K. Mishra et al., "Nickel germanide with rare earth interlayers for Ge CMOS applications," in Proc. IEEE Int. Conf. Electron Devices Solid-state Circuits (EDSSC), pp. 1-2, 2013. [66] Wilson, R. G. "Boron, fluorine, and carrier profiles for B and BF2 implants into crystalline and amorphous Si." Journal of applied physics 54.12. pp. 6879-6889, 1983. [67] J. Talvacchio, "Electrical contact to superconductors," IEEE Trans. Comp., Hybrids, Manuf. Technol., vol. 12, no. 1, pp. 21-31, 2002. [68] K. Gallacher, et al., "Ohmic contacts to n-type germanium with low specific contact resistivity," Appl. Phys. Lett., vol. 100, no. 2, 2012, Art. no. 022113. [69] R. Dormaier and S. E. Mohney, "Factors controlling the resistance of Ohmic contacts to n-InGaAs," J. Vac. Sci. Technol. B, vol. 30, no. 3, 2012, Art. no. 031209. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/102325 | - |
| dc.description.abstract | 隨著平面電晶體元件尺寸縮放逼近物理極限，量子穿隧效應使閘極漏電劇增，摩爾定律的延續除了走向元件結構及材料的創新，範式的轉移也是增加算力非常具前瞻性的策略。大規模量子計算架構開始由實驗室轉向商業化應用，開發能在極低溫環境下直接封裝於量子處理器旁的低溫電晶體（Cryo-CMOS）控制電路，已成為降低訊號延遲與解決熱負載瓶頸的關鍵要素。傳統互補式場效電晶體（CMOS）設計在極低溫下會遭遇顯著的物理性質偏差，針對各項參數提出基於物理的精簡模型將是成功設計低溫元件的基礎。因此本論文將著重在矽電晶體與接觸電阻元件的變溫特性，以幫助了解其低溫行為。
第二章彙整了近年對於半導體物理以及電晶體電性的低溫特性的發現，如載子凍結效應、臨界電壓飄移、次臨界擺幅飽和等現象，以及其可能的物理模型解釋。接著詳細記錄自行製作矽基電晶體的製作流程，並進行量測與分析。n型電晶體與p型電晶體在低溫皆出現臨界電壓上升與次臨界擺幅下降的趨勢，其中n型電晶體的結果觀察到在約50 K時飽和的現象，可用能帶尾態模型來解釋。電晶體效能表現的部分上，n型電晶體導通電流隨溫度下降而上升，同時聲子散射在低溫的下降也使電子遷移率出現3倍於室溫值的提升；p型電晶體卻顯示出相反的趨勢，顯示n型電晶體相對p型電晶體具有良好的介面品質與接觸電阻率，加上電洞較大的有效質量，使得p型電晶體的轉導與載子遷移率在低溫劣化。 第三章深入研究了接觸電阻的變溫特性。首先介紹金屬-半導體介面的基礎特性及量測方法，並整理不同文獻中優化室溫與低溫電阻率的可行方案，最後詳細描述RTLM量測架構的製作過程，並對鎳矽與鎳鍺介面的變溫量測及分析。鎳/n型矽與鎳/p型矽元件在低溫皆出現劣化的狀況，即使其較高的矽基板摻雜濃度，傳輸特性表現仍無法達到場發射（FE）模式，兩者分別呈現了熱場發射（TFE）與熱發射（TE）特徵，兩者在低溫都會因熱能被嚴重壓制而使接觸電阻率指數性飆升。而鎳/n型鍺元件雖具有相似溫度趨勢，但整體熱穩定度較高，從室溫到低溫始終維持在同一量級。 | zh_TW |
| dc.description.abstract | With large-scale quantum computers transition from laboratories to commercialization, the development of cryogenic CMOS (Cryo-CMOS) control circuits is critical for minimizing signal latency and overcoming thermal load constraints. However, conventional CMOS designs encounter significant physical deviations at cryogenic temperatures from room temperature. Establishing physics-based compact models is therefore essential for the successful design of cryogenic devices. Therefore, this thesis focuses on characteristic of Si MOSFETs and contact resistance under different temperatures for better understanding of their cryogenic behavior.
Chapter 2 introduces recent findings on cryogenic semiconductor physics and transistor electrical characteristics, including carrier freeze-out, threshold voltage shift, and subthreshold swing saturation, along with their underlying physical mechanisms. The fabrication process of silicon-based transistors is detailed, followed by comprehensive analysis and characterization. Both n-type and p-type transistors exhibit increased threshold voltage and reduced subthreshold swing at low temperatures. Notably, SS saturation in the n-type transistors occurs at approximately 50 K. Regarding device performance, the ON-current of n-type transistors improves as the temperature decreases due to reduced phonon scattering at low temperatures to enhances electron mobility. Conversely, p-type transistors show an opposing trend, which might be due to inferior interface quality and larger carrier effective mass. Chapter 3 investigates the temperature-dependent characteristics of contact resistance using a Refined Transmission Line Method (RTLM) structure. Analysis of Ni/Si and Ni/Ge interfaces reveals that Ni/n-Si and Ni/p-Si interfaces degrade at low temperatures. Despite high substrate doping levels, their transport characteristics fail to reach the Field Emission (FE) mode, instead exhibiting Thermionic Field Emission (TFE) and Thermionic Emission (TE) behavior. The suppressed thermal energy at low temperatures causes contact resistivity to increase exponentially. While Ni/n-Ge devices follow a similar trend, they demonstrate superior thermal stability, maintaining resistivity within the same order of magnitude from room temperature down to cryogenic levels. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2026-06-02T03:48:16Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2026-06-02T03:48:16Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 誌謝……………………………………………………………………………….. i
中文摘要………………………………………………………………………….. ii Abstract .………………………………………………………………………….. iv 目次……………………………………………………………………………….. vii 圖次……………………………………………………………………………….. ix 表次………………………………………………………………………………. xiii 第一章 引言…………………………………………………………………. 1 1.1 研究動機 …………………………………………………………........ 2 1.2低溫電晶體 ……………………………………………………………. 3 1.3 論文架構 ……………………………………………………………… 6 第二章 低溫電晶體………………………………………………………….. 7 2. 1低溫電晶體簡介 ………………………………………………………. 7 2.2 文獻回顧 ……………………………………………………………… 11 2.3 電晶體的製作 ………………………………………………………… 22 2.4 電晶體的變溫特性 …………………………………………………… 24 2.5 小結 ………………………………………………………………. 38 第三章 金屬/半導體之低溫接觸電阻特性 ………………………………….. 39 3.1接觸電阻簡介與量測方法 …………………………………………… 39 3.2 文獻回顧 ……………………………………………………………… 45 3.2.1 接觸電阻率的降低 ……………………………………………. 46 3.2.2 接觸電阻的低溫特性 …………………………………………. 51 3.3 鎳/矽與鎳/鍺接觸電阻的變溫特性 …………………………….… 58 3.4 小結 …………………………………………………………………… 67 第四章 結論與未來工作………………………………………………..…….. 69 4.1 結論 …………………………………………………………………… 69 4.2 未來工作 ……………………………………………………………… 70 參考文獻 …………………………………………………………………….…… 71 | - |
| dc.language.iso | zh_TW | - |
| dc.subject | Cryo-CMOS | - |
| dc.subject | 接觸電阻 | - |
| dc.subject | 量子計算 | - |
| dc.subject | Cryo-CMOS | - |
| dc.subject | Contact Resistance | - |
| dc.subject | Quantum Computing | - |
| dc.title | 矽金氧半電晶體與接觸電阻的變溫特性 | zh_TW |
| dc.title | Temperature Dependent Characteristic of Si Metal-Oxide-Semiconductor Field-Effect Transistors and Contact Resistance | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 114-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 李敏鴻;卓大鈞 | zh_TW |
| dc.contributor.oralexamcommittee | Min-Hung Lee;Ta-Chun Chou | en |
| dc.subject.keyword | Cryo-CMOS; 接觸電阻; 量子計算 | zh_TW |
| dc.subject.keyword | Cryo-CMOS; Contact Resistance; Quantum Computing | en |
| dc.relation.page | 77 | - |
| dc.identifier.doi | 10.6342/NTU202601026 | - |
| dc.rights.note | 同意授權(全球公開) | - |
| dc.date.accepted | 2026-05-12 | - |
| dc.contributor.author-college | 重點科技研究學院 | - |
| dc.contributor.author-dept | 元件材料與異質整合學位學程 | - |
| dc.date.embargo-lift | 2026-06-02 | - |
| dc.contributor.author-note | dept_res 2 uuid | - |
| 顯示於系所單位： | 元件材料與異質整合學位學程 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-114-2.pdf | 4.01 MB | Adobe PDF | 檢視/開啟 |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。