寬頻線性化降頻混頻器、應用於低軌道衛星通訊系統之功率放大器及 Ka 頻段氮化鎵功率放大器之研究

Abstract

本論文內容主要分為三個部分。第一部分為使用 90 奈米互補式金氧半導體製程所實現之具線性化架構的主動式巴倫寬頻降頻混頻器之設計與量測結果。第二部分為應用於低軌道衛星發射機的 Ku 頻段功率放大器，採用 0.18 微米砷化鎵偽晶高電子遷移率電晶體製程進行設計與實作。第三部分則為應用於 5G 通訊系統之38 GHz 高功率放大器，採用 0.12 微米氮化鎵高電子遷移率電晶體製程進行設計與量測。 在第一部分中，所提出的混頻器利用馬向巴倫提供寬頻差動射頻輸入訊號，並採用 NMOS 主動式負載以提升電路的線性度與輸出壓縮點。此外，於輸出端配置主動式巴倫以將低頻差動訊號轉換為單端輸出，並引入一組線性化輔助電路以進一步改善三階互調失真。量測結果顯示，該混頻器之最大轉換增益為 −4.6 dB，射頻頻寬範圍涵蓋36 至 88 GHz。當線性化輔助電路啟用時，IM3 可降低約 7 dB，證實其具有效的線性化效果。整體晶片含 pad 的面積為 0.38 mm²。 第二部分中，提出一個三級共源極架構之 Ku 頻段功率放大器，偏壓於 class AB 區域以兼顧增益、輸出功率與功率附加效率（PAE），並於訊號路徑串接小阻值電阻以提升穩定性。量測結果顯示，該功率放大器最大的小訊號增益為 25.8 dB， 3 dB 頻寬涵蓋 9.3 至 14.9 GHz；大訊號操作下輸出功率達 27.1 dBm，功率附加效率超過 30 %，晶片總面積為 2.28 mm²。 最後，第三部分提出一個兩級共源極架構之 38 GHz 高功率放大器，並將兩路放大器做功率合成以提升輸出功率。電路中驅動級偏壓於 class AB 以維持效率，功率級則偏壓於class A 以確保線性度與輸出功率。量測結果顯示，此功率放大器具有 20.7 dB 小訊號增益，於 38 GHz 輸出功率達 36.2 dBm，功率附加效率為 31.3 %，晶片面積為 5 mm²。

This thesis consists of three parts. The first part presents the design and measurement results of a broadband down-conversion mixer with linearity-improved active IF balun, implemented in a 90-nm CMOS process. The second part describes a Ku-band power amplifier designed and fabricated in a 0.18-µm GaAs pseudomorphic high electron mobility transistor (pHEMT) process for low-Earth-orbit (LEO) satellite transmitters. The third part introduces a 38-GHz high-power amplifier implemented in a 0.12-µm GaN high electron mobility transistor (HEMT) process for 5G communication systems. In the first part, the proposed down-conversion mixer employs a Marchand balun to generate a wideband differential RF signal, while an NMOS active load is utilized to improve linearity and the input 1-dB compression point (IP1dB). An active balun at the output converts the low-frequency differential signal into a single-ended output, and an auxiliary linearization circuit is introduced to further suppress third-order intermodulation (IM3). Measurement results show that the proposed mixer achieves a maximum conversion gain of −4.6 dB with an RF bandwidth extending from 36 to 88 GHz. With the auxiliary circuit enabled, IM3 is reduced by approximately 7 dB, demonstrating effective linearity enhancement. The total chip area, including pads, is 0.38 mm². In the second part, a three-stage common-source Ku-band power amplifier is presented. The amplifier operates in class-AB bias to achieve a good balance among gain, output power, and power-added efficiency (PAE), with small series resistors inserted along the signal path for stability improvement. Measurement results indicate a maximum small-signal gain of 25.8 dB, a 3-dB bandwidth from 9.3 GHz to 14.9 GHz, a saturated output power of approximately 27.1 dBm, and a PAE exceeding 30 %. The total chip area is 2.28 mm². The third part presents a 38-GHz high-power amplifier employing a two-stage common-source configuration with 2-ways power combining. The driver stage is biased in class-AB to maintain high efficiency, while the power stage operates in class-A to ensure high output power and linearity. Measurement results demonstrate a small-signal gain of 20.7 dB, a saturated output power of 36.2 dBm at 38 GHz, and a power-added efficiency of 31.3 %. The overall chip area is 5 mm².