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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/99644| 標題: | 不同結構參數調變之碳化矽平面金氧半場效電晶體於高溫閘極偏壓下之電性參數分析 Electrical Parameters Analysis of SiC Planar MOSFET with Structural Variations under High-Temperature Gate Bias Stress |
| 作者: | 盧采裴 Tsai-Pei Lu |
| 指導教授: | 李坤彥 Kung-Yen Lee |
| 關鍵字: | 碳化矽,平面式金氧半場效電晶體,閘極氧化層,高溫閘極偏壓,功率循環測試,閥值電壓,導通電阻, Silicon Carbide (SiC),Power MOSFET,Gate Oxide,High-Temperature Gate Bias (HTGB),Power Cycling Test (PCT),Threshold Voltage (Vth),On-Resistance (Rds,on), |
| 出版年 : | 2025 |
| 學位: | 碩士 |
| 摘要: | 隨著電動車與再生能源等高功率應用迅速發展,具備高壓、高溫與高頻操作能力的碳化矽 (SiC) 功率元件已成為次世代能源轉換技術的關鍵。然而,SiC MOSFET 的長期可靠度仍受限於其氧化層與介面缺陷問題,特別是在高溫閘極偏壓 (HTGB) 與熱循環應力 (PCT) 條件下,易產生閾值電壓漂移、導通電阻上升與閘極電容變化等現象。
本研究選用三種結構不同的1200V平面型SiC MOSFET元件,透過長時間HTGB與直流功率循環測試,系統性分析包括Vth、Rds,on、VSD、Cg–Vg、VFB與Qg等電性參數之劣化行為。結果顯示,正HTGB造成電子陷阱累積,導致Vth上升與Cg–Vg右移,而負HTGB則呈現Vth初升後下降的雙階段機制,反映電洞捕獲與電荷釋放的交互影響。PCT測試中,元件因熱–機械應力交互應力產生明顯的Rds,on增加與Vth漂移,且結構設計如通道長度 (Lch) 、側壁寬度 (Sidewall) 與源極接觸重疊 (Lcont) 對劣化程度具明確關聯。 研究結果不僅揭示SiC MOSFET在靜態與動態應力下的退化行為,亦建立了結構參數與可靠度表現之對應關係。此成果可作為未來高可靠度元件設計與壽命預測的實證基礎,對於車用、高頻與極端環境應用中之SiC元件開發具高度參考價值。 With the rapid growth of electric vehicles and renewable energy systems, Silicon Carbide (SiC) power MOSFETs have emerged as essential components due to their superior high-voltage, high-temperature, and high-frequency capabilities. However, long-term reliability remains a critical challenge, particularly under High-Temperature Gate Bias (HTGB) and Power Cycling Test (PCT) conditions, where gate oxide degradation and interface instability can induce threshold voltage shifts, increased on-resistance, and altered gate capacitance. This work investigates the degradation behaviors of three 1200 V planar SiC MOSFETs with varying structural parameters under prolonged HTGB and PCT stresses. Key electrical characteristics including Vth, Rds,on, VSD, Cg–Vg, VFB, and Qg were analyzed. Under positive HTGB, electron trapping causes Vth increase and Cg–Vg right-shift, while negative HTGB reveals a two-stage Vth behavior driven by hole capture and interface charge release. PCT results indicate stress-induced Rds,on increase and Vth drift due to thermal–mechanical fatigue, with structural factors such as channel length (Lch), sidewall width, and source contact length (Lcont) playing critical roles in degradation severity. The findings provide a comprehensive correlation between device structure and reliability performance under combined electrical and thermal stresses. This study not only clarifies key degradation mechanisms but also offers practical guidelines for future SiC MOSFET design targeting high-reliability automotive and high-frequency applications. |
| URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/99644 |
| DOI: | 10.6342/NTU202503743 |
| 全文授權: | 未授權 |
| 電子全文公開日期: | N/A |
| 顯示於系所單位: | 工程科學及海洋工程學系 |
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| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-113-2.pdf 未授權公開取用 | 2.27 MB | Adobe PDF |
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