透過背閘極高介電常數基板預處理優化二硒化鎢P型場效電晶體

Abstract

本研究針對單層二硒化鎢所構成之增強型電洞載子全局背閘極場效電晶體以及雙閘極場效電晶體進行製程開發與電性優化，並探討高介電常數閘極氧化層的品質與雙閘極結構對元件開關性能的影響。 本作的背閘極基板為氮化鈦做為閘極基底，其上方是以原子層沉積製備之八奈米厚的二氧化鉿作為背閘極氧化層，本作將透過氮氫混和氣體退火與氧電漿進行氧化層預處理，用以提升背閘極氧化層及其作為高介電常數氧化層與二維材料介面的品質。緊接著使用濕式轉移法將單層二硒化鎢轉移至經過預處理的目標基板上，並以光微影技術定義源極/汲極之電極與上電極圖案，完成具全局背閘極與上閘極的雙閘極電晶體結構。 經實驗結果顯示，經氧化層預處理之二氧化鉿基板能有效降低界面態密度，使得元件的次臨界擺幅、臨界電壓、遲滯與導通電流皆有明顯改善。在進一步導入上閘極後，在不犧牲其他電性表現的前提下，得益於雙閘極良好的協作以及更優異的閘極控制能力，使得元件能夠在臨界電壓往更理想的方向推動，並且在次臨界區的擺幅能夠進一步下降，展現出良好的雙閘極調控效果。 本研究結果證明，藉由介面預處理優化與閘極堆疊的工程，能夠有效提升單層二硒化鎢電晶體整體的電性表現，為二維材料於低功耗邏輯元件之應用提供新的方向與參考。

This study develops fabrication processes for p-type enhancement-mode global back-gate FETs and dual-gate FETs based on monolayer WSe₂, and evaluates how high-k gate-oxide quality and dual-gate architecture influence switching performance. Devices use TiN as the back-gate electrode with an 8 nm HfO₂ dielectric deposited by ALD, followed by forming-gas annealing and O₂-plasma pre-treatments to improve oxide quality and the WSe₂/oxide interface. A monolayer WSe₂ is wet-transferred onto the treated substrate, and optical lithography defines the source/drain contacts and a local top gate, forming a dual-gate structure. Pre-treated HfO₂ markedly lowers interface-trap density, yielding better subthreshold swing, threshold voltage, hysteresis, and on-current. Adding the top gate further strengthens electrostatic control without sacrificing other metrics: the threshold voltage moves closer to the ideal case and the subthreshold swing further improves, demonstrating effective dual-gate modulation. These results show that interface pre-treatment combined with gate-stack engineering can significantly enhance monolayer WSe₂ transistor performance, providing guidelines and benchmarks for low-power logic applications based on 2-D materials.