請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/98933完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳志毅 | zh_TW |
| dc.contributor.advisor | Chih-I Wu | en |
| dc.contributor.author | 邱英展 | zh_TW |
| dc.contributor.author | Ying-Zhan Chiu | en |
| dc.date.accessioned | 2025-08-20T16:20:25Z | - |
| dc.date.available | 2025-08-21 | - |
| dc.date.copyright | 2025-08-20 | - |
| dc.date.issued | 2025 | - |
| dc.date.submitted | 2025-08-13 | - |
| dc.identifier.citation | [1] T. Wei, Z. Han, X. Zhong, Q. Xiao, T. Liu, and D. Xiang, "Two dimensional semiconducting materials for ultimately scaled transistors," Science, vol. 25, no. 10, 2022.
[2] S. Wang, X. Liu, and P. Zhou, "The road for 2D semiconductors in the silicon age," Advanced Materials, vol. 34, no. 48, p. 2106886, 2022. [3] K. S. Kim et al., "The future of two-dimensional semiconductors beyond Moore’s law," Nature Nanotechnology, vol. 19, no. 7, pp. 895-906, 2024. [4] J. Matson, "Graphene researchers Geim and Novoselov win Nobel Prize in Physics," Scientific American, vol. 6, 2010. [5] M. Chhowalla, D. Jena, and H. Zhang, "Two-dimensional semiconductors for transistors," Nature Reviews Materials, vol. 1, no. 11, pp. 1-15, 2016. [6] K. S. Novoselov, A. Mishchenko, A. Carvalho, and A. Castro Neto, "2D materials and van der Waals heterostructures," Science, vol. 353, no. 6298, p. aac9439, 2016. [7] W. Cao et al., "The future transistors," Nature, vol. 620, no. 7974, pp. 501-515, 2023. [8] Q. H. Wang, K. Kalantar-Zadeh, A. Kis, J. N. Coleman, and M. S. Strano, "Electronics and optoelectronics of two-dimensional transition metal dichalcogenides," Nature nanotechnology, vol. 7, no. 11, pp. 699-712, 2012. [9] P. Tonndorf et al., "Photoluminescence emission and Raman response of monolayer MoS2, MoSe2, and WSe2," Optics express, vol. 21, no. 4, pp. 4908-4916, 2013. [10] H. Sahin et al., "Anomalous Raman spectra and thickness-dependent electronic properties of WSe2," Physical Review B—Condensed Matter and Materials Physics, vol. 87, no. 16, p. 165409, 2013. [11] Q. Cheng et al., "WSe2 2D p‐type semiconductor‐based electronic devices for information technology: design, preparation, and applications," InfoMat, vol. 2, no. 4, pp. 656-697, 2020. [12] Y.-H. Chen et al., "P-Type Ohmic Contact to Monolayer WSe2 Field-Effect Transistors Using High-Electron Affinity Amorphous MoO3," ACS Applied Electronic Materials, vol. 4, no. 11, pp. 5379-5386, 2022. [13] T. Irisawa, "Two-dimensional material transistors: Expectations observed in the IRDS road map and latest research progresses," JSAP Review, vol. 2024, p. 240307, 2024. [14] J. Liu, Y. Zhou, and W. Zhu, "Dielectric-induced interface states in black phosphorus and tungsten diselenide capacitors," Applied Physics Letters, vol. 113, no. 1, 2018. [15] H.-Y. Lan et al., "Improved Hysteresis of High-Performance p-Type WSe2 Transistors with Native Oxide WOx Interfacial Layer," Nano Letters, vol. 25, no. 14, pp. 5616-5623, 2025 [16] H.-Y. Lan et al., "Reliability of high-performance monolayer MoS2 transistors on scaled high-k HfO2," npj 2D Materials and Applications, vol. 9, no. 1, p. 5, 2025. [17] H. A. Hsain et al., "Many routes to ferroelectric HfO2: A review of current deposition methods," Journal of Vacuum Science & Technology A, vol. 40, no. 1, 2022. [18] U. Schroeder, M. H. Park, T. Mikolajick, and C. S. Hwang, "The fundamentals and applications of ferroelectric HfO2," Nature Reviews Materials, vol. 7, no. 8, pp. 653-669, 2022. [19] A. Bazigos, M. Bucher, J. Assenmacher, S. Decker, W. Grabinski, and Y. Papananos, "An adjusted constant-current method to determine saturated and linear mode threshold voltage of MOSFETs," IEEE Transactions on Electron Devices, vol. 58, no. 11, pp. 3751-3758, 2011. [20] G. Bersuker, P. Zeitzoff, G. Brown, and H. Huff, "Dielectrics for future transistors," Materials Today, vol. 7, no. 1, pp. 26-33, 2004. [21] Y. Pan et al., "Near-ideal subthreshold swing MoS2 back-gate transistors with an optimized ultrathin HfO2 dielectric layer," Nanotechnology, vol. 30, no. 9, p. 095202, 2019. [22] J. Gavartin, A. Shluger, A. S. Foster, and G. Bersuker, "The role of nitrogen-related defects in high-k dielectric oxides: Density-functional studies," Journal of applied physics, vol. 97, no. 5, 2005. [23] K. Han, X. Ma, J. Xiang, H. Yang, and W. Wang, "Effect of low temperature annealing on the electrical properties of an MOS capacitor with a HfO2 dielectric and a TiN metal gate," Journal of Semiconductors, vol. 34, no. 11, p. 114007, 2013. [24] P. Zhao et al., "Effects of annealing on top-gated MoS2 transistors with HfO2 dielectric," Journal of Vacuum Science & Technology B, vol. 35, no. 1, 2017. [25] W. Weinreich et al., "Detailed leakage current analysis of metal–insulator–metal capacitors with ZrO2, ZrO2/SiO2/ZrO2, and ZrO2/Al2O3/ZrO2 as dielectric and TiN electrodes," Journal of Vacuum Science & Technology B, vol. 31, no. 1, 2013. [26] P. Zhao et al., "Understanding the impact of annealing on interface and border traps in the Cr/HfO2/Al2O3/MoS2 system," ACS Applied Electronic Materials, vol. 1, no. 8, pp. 1372-1377, 2019. [27] Y. Y. Illarionov et al., "Insulators for 2D nanoelectronics: the gap to bridge," Nature communications, vol. 11, no. 1, p. 3385, 2020. [28] K.-C. Liu, J.-R. Tsai, W.-K. Lin, C.-S. Li, and J.-N. Chen, "Defect passivation by O2 plasma treatment on high-k dielectric HfO2 films at room temperature," Thin Solid Films, vol. 519, no. 15, pp. 5110-5113, 2011. [29] M. Januar, S. P. Prakoso, S.-Y. Lan, R. K. Mahanty, S.-Y. Kuo, and K.-C. Liu, "The role of oxygen plasma in the formation of oxygen defects in HfO x films deposited at room temperature," Journal of Materials Chemistry C, vol. 3, no. 16, pp. 4104-4114, 2015. [30] A.-S. Chou et al., “Performance Step-up in PMOS with Monolayer WSe2 Channel,” In 2025 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits); IEEE, 2025 [31] J. Sim et al., "Effects of ALD HfO2 thickness on charge trapping and mobility," Microelectronic Engineering, vol. 80, pp. 218-221, 2005. [32] P. Bolshakov et al., "Dual-gate MoS2 transistors with sub-10 nm top-gate high-k dielectrics," Applied Physics Letters, vol. 112, no. 25, 2018. [33] H. C. Movva et al., "High-mobility holes in dual-gated WSe2 field-effect transistors," ACS nano, vol. 9, no. 10, pp. 10402-10410, 2015. [34] W. Chakraborty et al., "Higher-k zirconium doped hafnium oxide (HZO) trigate transistors with higher DC and RF performance and improved reliability," in 2021 Symposium on VLSI Technology, 2021: IEEE, pp. 1-2 [35] W. Fei, J. Trommer, M. C. Lemme, T. Mikolajick, and A. Heinzig, "Emerging reconfigurable electronic devices based on two‐dimensional materials: A review," InfoMat, vol. 4, no. 10, p. e12355, 2022. [36] S. Das et al., "Transistors based on two-dimensional materials for future integrated circuits," Nature Electronics, vol. 4, no. 11, pp. 786-799, 2021. [37] H. Liu and D. Y. Peide, "Dual-Gate MOSFET With Atomic-Layer-Deposited Al2O3 as Top-Gate Dielectric," IEEE electron device letters, vol. 33, no. 4, pp. 546-548, 2012. [38] N. Fang and K. Nagashio, "Band tail interface states and quantum capacitance in a monolayer molybdenum disulfide field-effect-transistor," Journal of Physics D: Applied Physics, vol. 51, no. 6, p. 065110, 2018. [39] A. Gaur, T. Agarwal, I. Asselberghs, I. Radu, M. Heyns, and D. Lin, "A MOS capacitor model for ultra-thin 2D semiconductors: the impact of interface defects and channel resistance," 2D Materials, vol. 7, no. 3, p. 035018, 2020. [40] A. Gaur et al., "Demonstration of 2e12 cm− 2 eV− 1 2D-oxide interface trap density on back-gated MoS2 flake devices with 2.5 nm EOT," Microelectronic Engineering, vol. 178, pp. 145-149, 2017. [41] R. K. Bennett, D. Yin, and Y. Yoon, "Assessing the role of a semiconductor’s anisotropic permittivity in hafnium disulfide monolayer field-effect transistors," IEEE Transactions on Electron Devices, vol. 67, no. 6, pp. 2607-2613, 2020. [42] A. Pal, T. Chavan, J. Jabbour, W. Cao, and K. Banerjee, "Three-dimensional transistors with two-dimensional semiconductors for future CMOS scaling," Nature Electronics, vol. 7, no. 12, pp. 1147-1157, 2024. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/98933 | - |
| dc.description.abstract | 本研究針對單層二硒化鎢所構成之增強型電洞載子全局背閘極場效電晶體以及雙閘極場效電晶體進行製程開發與電性優化，並探討高介電常數閘極氧化層的品質與雙閘極結構對元件開關性能的影響。
本作的背閘極基板為氮化鈦做為閘極基底，其上方是以原子層沉積製備之八奈米厚的二氧化鉿作為背閘極氧化層，本作將透過氮氫混和氣體退火與氧電漿進行氧化層預處理，用以提升背閘極氧化層及其作為高介電常數氧化層與二維材料介面的品質。緊接著使用濕式轉移法將單層二硒化鎢轉移至經過預處理的目標基板上，並以光微影技術定義源極/汲極之電極與上電極圖案，完成具全局背閘極與上閘極的雙閘極電晶體結構。 經實驗結果顯示，經氧化層預處理之二氧化鉿基板能有效降低界面態密度，使得元件的次臨界擺幅、臨界電壓、遲滯與導通電流皆有明顯改善。在進一步導入上閘極後，在不犧牲其他電性表現的前提下，得益於雙閘極良好的協作以及更優異的閘極控制能力，使得元件能夠在臨界電壓往更理想的方向推動，並且在次臨界區的擺幅能夠進一步下降，展現出良好的雙閘極調控效果。 本研究結果證明，藉由介面預處理優化與閘極堆疊的工程，能夠有效提升單層二硒化鎢電晶體整體的電性表現，為二維材料於低功耗邏輯元件之應用提供新的方向與參考。 | zh_TW |
| dc.description.abstract | This study develops fabrication processes for p-type enhancement-mode global back-gate FETs and dual-gate FETs based on monolayer WSe₂, and evaluates how high-k gate-oxide quality and dual-gate architecture influence switching performance. Devices use TiN as the back-gate electrode with an 8 nm HfO₂ dielectric deposited by ALD, followed by forming-gas annealing and O₂-plasma pre-treatments to improve oxide quality and the WSe₂/oxide interface. A monolayer WSe₂ is wet-transferred onto the treated substrate, and optical lithography defines the source/drain contacts and a local top gate, forming a dual-gate structure.
Pre-treated HfO₂ markedly lowers interface-trap density, yielding better subthreshold swing, threshold voltage, hysteresis, and on-current. Adding the top gate further strengthens electrostatic control without sacrificing other metrics: the threshold voltage moves closer to the ideal case and the subthreshold swing further improves, demonstrating effective dual-gate modulation. These results show that interface pre-treatment combined with gate-stack engineering can significantly enhance monolayer WSe₂ transistor performance, providing guidelines and benchmarks for low-power logic applications based on 2-D materials. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-08-20T16:20:25Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2025-08-20T16:20:25Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 致謝 i
中文摘要 ii ABSTRACT iii 目次 iv 圖次 vii 表次 x Chapter 1 緒論 1 1.1 半導體發展概述 1 1.1.1 摩爾定律與元件微縮挑戰 1 1.1.2 製程技術演進 2 1.2 二維材料介紹 3 1.2.1 二維材料應用潛力 4 1.2.2 過度金屬二硫族化物簡介 5 1.2.3 單層二硒化鎢特性 8 1.3 實驗動機 11 1.3.1 高介電常數基板 11 1.3.2 介面問題 13 Chapter 2 實驗方法與理論 16 2.1 製程儀器 16 2.1.1 原子層沉積系統 16 2.1.2 快速熱退火系統 17 2.1.3 氧電漿機 18 2.1.4 無光罩步進式曝光機 19 2.1.5 電子束蒸鍍機 21 2.1.6 感應耦合電漿蝕刻 22 2.2 量測儀器 23 2.2.1 光致發光及拉曼光譜儀 23 2.2.2 原子力顯微鏡 24 2.2.3 電性量測系統 25 2.2.4 穿透式電子顯微鏡 26 2.3 單層二硒化鎢溼式轉移法 27 2.4 平行板電容器參數萃取 28 2.5 場效電晶體參數萃取 29 2.5.1 臨界電壓 29 2.5.2 次臨界擺幅 30 2.5.3 場效遷移率 31 2.6 背閘極場效電晶體製程 32 Chapter 3 氧化層預處理 33 3.1 混和氣體熱退火處理 (Forming Gas Annealing) 34 3.1.1 理論基礎 34 3.1.2 平行板電容器分析 38 3.1.3 背閘極場效電晶體分析 41 3.2 氧電漿處理 (O2 plasma) 44 3.2.1 理論基礎 44 3.2.2 背閘極場效電晶體 47 3.3 表面分析 (Surface analysis) 51 3.3.1 原子力顯微鏡分析 51 3.4 雙步驟處理 (two-steps treatment) 53 3.4.1 電性對比 53 3.4.2 等效氧化層厚度 55 Chapter 4 雙閘極電晶體 58 4.1 上閘極製程討論 59 4.1.1 上閘極氧化層 59 4.1.2 上閘極製程 61 4.2 雙閘極電晶體 62 4.3 上閘極等效氧化層厚度 65 4.4 穿透式電子顯微鏡分析 68 Chapter 5 結論與未來展望 70 5.1 總結 70 5.2 未來方向 70 REFERENCE 72 | - |
| dc.language.iso | zh_TW | - |
| dc.subject | 二硒化鎢 | zh_TW |
| dc.subject | 二維材料 | zh_TW |
| dc.subject | 雙閘極場效電晶體 | zh_TW |
| dc.subject | 增強型空洞載子場效電晶體 | zh_TW |
| dc.subject | 等效氧化層厚度微縮 | zh_TW |
| dc.subject | Equivalent oxide thickness scaling | en |
| dc.subject | Dual gate Field effect transistor | en |
| dc.subject | P-type Field effect transistor | en |
| dc.subject | Two-dimensional materials | en |
| dc.subject | Tungsten diselenide | en |
| dc.title | 透過背閘極高介電常數基板預處理優化二硒化鎢P型場效電晶體 | zh_TW |
| dc.title | Optimization of WSe2 P-Type FET through Back Gate High-k Substrate Pretreatment | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 周昂昇;張子璿;陳奕君;楊伯康 | zh_TW |
| dc.contributor.oralexamcommittee | Ang-Sheng Chou;Tzu-Hsuan Chang;I-Chun Cheng;Po-Kang Yang | en |
| dc.subject.keyword | 二維材料,二硒化鎢,等效氧化層厚度微縮,增強型空洞載子場效電晶體,雙閘極場效電晶體, | zh_TW |
| dc.subject.keyword | Two-dimensional materials,Tungsten diselenide,Equivalent oxide thickness scaling,P-type Field effect transistor,Dual gate Field effect transistor, | en |
| dc.relation.page | 76 | - |
| dc.identifier.doi | 10.6342/NTU202504002 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2025-08-15 | - |
| dc.contributor.author-college | 重點科技研究學院 | - |
| dc.contributor.author-dept | 元件材料與異質整合學位學程 | - |
| dc.date.embargo-lift | N/A | - |
| 顯示於系所單位： | 元件材料與異質整合學位學程 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-113-2.pdf 未授權公開取用 | 5.72 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。