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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李俊興 | zh_TW |
| dc.contributor.advisor | Chun-Hsing Li | en |
| dc.contributor.author | 林品妤 | zh_TW |
| dc.contributor.author | Pin-Yu Lin | en |
| dc.date.accessioned | 2025-08-19T16:15:00Z | - |
| dc.date.available | 2025-08-20 | - |
| dc.date.copyright | 2025-08-19 | - |
| dc.date.issued | 2025 | - |
| dc.date.submitted | 2025-08-06 | - |
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Nagabushanam, "A 2.4GHz CMOS Double Balanced Down Conversion Gilbert Cell Mixer Design Using 180nm Technology," 2018 3rd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT), Bangalore, India, 2018, pp. 1767-1770. [21] D. Parveg, M. Varonen, M. Kärkkäinen, D. Karaca, A. Vahdati and K. A. I. Halonen, "Wideband millimeter-wave active and passive mixers in 28 nm bulk CMOS technology," 2015 10th European Microwave Integrated Circuits Conference (EuMIC), Paris, France, 2015, pp. 116-119. [22] M. R. Nikbakhsh, A. Jannesari, E. Abiri and S. Salem, "A Double Balanced Mixer with Folded Structure and Variable-Conversion gain in 65nm CMOS," 2020 28th Iranian Conference on Electrical Engineering (ICEE), Tabriz, Iran, 2020, pp. 1-5. [23] E. S. Atalla, F. Zhang, A. Bellaouar and P. T. Balsara, "Estimation of passive mixer output bandwidth using switched-capacitor techniques," Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, San Jose, CA, USA, 2013, pp. 1-4. [24] X. Lv and C. Zhang, "Design of A CML Driver Circuit in 28 nm CMOS Process," 2018 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), Chengdu, China, 2018, pp. 9-12. [25] M. W. Allam and M. I. Elmasry, "Dynamic current mode logic (DyCML): a new low-power high-performance logic style," in IEEE Journal of Solid-State Circuits, vol. 36, no. 3, pp. 550-558, March 2001. [26] H. Hassan, M. Anis and M. Elmasry, "MOS current mode circuits: analysis, design, and variability," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 8, pp. 885-898, Aug. 2005. [27] G. Scotti, D. Bellizia, A. Trifiletti and G. Palumbo, "Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 12, pp. 3509-3520, Dec. 2017. [28] M. Sakare and S. Gupta, "A high-speed PRBS generator using flip-flops employing feedback for distributed equalization," 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, VIC, Australia, 2014, pp. 746-749. [29] R. Singh and K. S. Pande, "4-bit Counter Using High-Speed Low-Voltage CML D-Flipflops," 2018 3rd International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, 2018. [30] M. Sakare, M. Singh, and S. Gupta, “A 4 × 20 Gb/s 29−1 PRBS Generator for Testing a High-Speed DAC in 90nm CMOS Technology,” Progress in VLSI Design and Test (VDAT), 2012. [31] P. Singh, M. K. Singh, V. G. Hande and M. Sakare, "Design of a PRBS generator and a serializer using active inductor employed CML latch," 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Lansing, MI, USA, 2021, pp. 802-805. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/98799 | - |
| dc.description.abstract | 隨著未來第六代（6G）無線通訊系統快速發展，系統運作頻率逐漸提升至毫米波甚至太赫茲頻段，對於超高速且高可靠度的資料傳輸需求也日益增加。為了滿足這些要求，先進的相位陣列發射器技術變得越來越重要。
本論文設計並實作了兩個關鍵模組，分別為注入鎖定式相位調變電路以及用於校正的偽隨機位元序列（PRBS）產生器，以支援高頻相位陣列系統的應用。這兩個電路分別獨立實現，各自展現了新一代毫米波與太赫茲無線系統中所需的重要功能。 相位調變電路採用可調元件來降低製程變異的影響，並在佈局上考量對稱性與訊號損耗的最小化。為了協助訊號量測與輸出，整合了取樣器、混波器與電流模式邏輯（CML）緩衝器等週邊電路。此電路成功在60 GHz下實現相位調變功能，頻率調整範圍約為2.6 GHz，鎖定範圍超過7 GHz，並可達約2ns的快速穩定時間。 在高速數位訊號產生的部分，PRBS產生器使用適用於高頻操作的CML邏輯閘設計，達到四通道、每通道30 Gbps的輸出速度。模擬結果顯示，在15 GHz時脈下能穩定運作，確保輸出高品質的偽隨機位元序列，可作為調變與校正所需的資料來源。 儘管這兩個電路為分別的設計，但各自解決了在相位陣列發射器中的關鍵挑戰。其中注入鎖定電路可提供精確的相位控制，而PRBS電路則支援所需的高速資料產生。兩者的實現為未來可擴展的波束成形架構與進階數位調變技術打下了良好基礎，有助於推動下一代無線通訊技術的發展。 | zh_TW |
| dc.description.abstract | With the rapid advancement of future 6G wireless communication systems operating in the millimeter-wave and terahertz frequency bands, there is a growing demand for ultra-high-speed and highly reliable data transmission. To address these challenges, advanced phased-array transmitter technologies have become increasingly essential.
This thesis presents the design and implementation of two key modules, an injection-locked phase modulation circuit and a pseudo-random bit sequence (PRBS) generator for calibration, which support high-frequency phased-array transmitter systems. The two circuits were developed independently, and each demonstrates important capabilities required for next-generation millimeter-wave and terahertz communication platforms. The injection-locked phase modulation circuit incorporates tunable components to mitigate process variations, and layout techniques such as symmetry and loss minimization are carefully applied. Supporting circuits, including samplers, mixers, and current-mode logic (CML) buffers, are integrated to enable precise signal interfacing and accurate measurement. The phase modulation function has been verified at 60 GHz, achieving a tuning range of approximately 2.6 GHz, a locking range greater than 7 GHz, and a fast settling time of around 2 ns. To enable high-speed digital pattern generation for modulation, a four-lane PRBS generator was designed using CML logic gates optimized for high-frequency operation. Each lane operates at 30 Gbps, and simulation results confirm that the circuit performs reliably at a 15 GHz clock frequency. The PRBS generator ensures stable output of high-quality pseudo-random bit streams for calibration use. Although these two modules are implemented separately, they individually address critical aspects of phased-array transmitter design. The injection-locked circuit enables precise phase control, while the PRBS generator provides the necessary high-speed data patterns. Together, these contributions lay the groundwork for scalable beamforming systems and advanced modulation techniques that support the development of next-generation wireless communication technologies. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-08-19T16:15:00Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2025-08-19T16:15:00Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 口試委員會審定書 i
誌謝 ii 中文摘要 iii ABSTRACT iv CONTENTS vi LIST OF FIGURES ix LIST OF TABLES xi Chapter 1 Introduction 1 1.1 Wireless Transmitters in mm-Wave and THz Bands 1 1.2 Injection-Locked Based Architectures 3 1.3 Proposed Phased-Array Transmitter Architecture 5 Chapter 2 A 60-GHz Phase-Modulated Circuit 7 2.1 System Architecture 7 2.2 Fundamentals of Voltage-Controlled Oscillator (VCO) 9 2.2.1 Design Considerations 9 2.2.2 Design of LC tank 10 2.3 Proposed Injection-Locked Phase Modulation Circuit 14 2.3.1 Theory of Injection Locking 14 2.3.2 Digital Current Control for Injection-Locked Oscillator 17 2.3.3 Frequency Tuning and Locking Range Characterization 20 2.3.4 Phase Shift Performance and Locking Settling Time 22 2.4 Phase Detector (PD) 24 2.4.1 Switched Capacitor 24 2.4.2 Sampler-based Phase Detector 27 2.4.3 Fundamentals of Mixer 31 2.4.4 Mixer-based Phase Detector 35 2.4.5 Comparison 41 2.5 Current-Mode Logic 43 2.5.1 Fundamentals of Differential Pair 43 2.5.2 Design Considerations 47 2.5.3 Design of Proposed Current Mode Logic Buffer 50 2.6 Measurement Results 55 2.6.1 Chip Micrograph and Measurement Setup 55 2.6.2 PCB Design 59 2.6.3 Free-running VCO measurement 62 2.6.4 Injection-locked VCO locking range and settling time analysis 64 Chapter 3 A 4×30 Gbps Pseudo-Random Binary Sequence Generator 70 3.1 System Architecture 70 3.2 Fundamentals of Phase Shifter Calibration 72 3.2.1 Data Pattern Generation for Phase Shifter Control 72 3.2.2 High-Speed PRBS Circuit Considerations 73 3.3 Design and Analysis of CML-Based Logic Blocks 74 3.3.1 Proposed CML-Based D Flip-Flop 74 3.3.2 Proposed CML-based XOR Circuit 78 3.3.3 Proposed CML-based MUX Circuit 79 3.3.4 PRBS Generator Integration and Performance Verification 80 Chapter 4 Conclusions 81 Chapter 5 Future Works 82 REFERENCE 83 | - |
| dc.language.iso | en | - |
| dc.subject | 相位調變電路 | zh_TW |
| dc.subject | 偽隨機二進位序列產生器 | zh_TW |
| dc.subject | 注入鎖定振盪器 | zh_TW |
| dc.subject | PRBS Generator | en |
| dc.subject | Phase Modulation Circuit | en |
| dc.subject | Injection-Locked Oscillator | en |
| dc.title | 用於校正之注入鎖定相位調變電路與PRBS產生器之設計 | zh_TW |
| dc.title | Design of an Injection-Locked Phase Modulation Circuit and a PRBS Generator for Calibration | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.coadvisor | 簡俊超 | zh_TW |
| dc.contributor.coadvisor | Jun-Chau Chien | en |
| dc.contributor.oralexamcommittee | 鄭宇翔;廖育德 | zh_TW |
| dc.contributor.oralexamcommittee | Yu-Hsiang Cheng;Yu-Te Liao | en |
| dc.subject.keyword | 相位調變電路,注入鎖定振盪器,偽隨機二進位序列產生器, | zh_TW |
| dc.subject.keyword | Phase Modulation Circuit,Injection-Locked Oscillator,PRBS Generator, | en |
| dc.relation.page | 87 | - |
| dc.identifier.doi | 10.6342/NTU202504032 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2025-08-12 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | N/A | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-113-2.pdf 未授權公開取用 | 3.57 MB | Adobe PDF |
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