應用高介電常數場板氧化層之橫向雙擴散金氧半場效電晶體最佳化

Abstract

隨著電源管理及高速介面電路對於高效率、高可靠度的要求日益嚴苛，橫向雙擴散金氧半場效電晶體 (Lateral Double-Diffused MOSFET, LDMOS) 已成為現代雙極性接面電晶體-互補式金屬氧化物半導體-雙擴散金屬氧化物半導體 (Bipolar-CMOS-DMOS, BCD) 製程中不可或缺的關鍵元件。傳統 LDMOS 場板結構多以二氧化矽 (SiO2) 作為場板氧化層，其介電常數約為3.9，因此對漂移區的電場分佈調控能力有限，難以達到更佳的元件性能。過去文獻提出將高介電常數 (High-k, HK) 材料用於場板氧化層，藉由改善電場分佈來提升崩潰電壓 (Breakdown Voltage, BV) 並降低特徵導通電阻 (Specific On-State Resistance, Ron,sp)。然而，HK 材料之應用大多聚焦於高壓 (BV > 100 V) 應用，且多以鈣鈦礦材料為主，存在晶格不匹配與界面電荷等問題，限制其與 CMOS 製程的相容性及可靠度。並且，過往文獻中缺乏對於場板連接方式進行系統性的探討。因此，本研究將著重於低壓 (BV ≈ 40 V) 應用，採用與CMOS製程相容性高之二氧化鉿 (HfO2, k ≈ 22) 作為場板氧化層，並系統性分析不同場板連接策略，包含閘極連接、浮接與源極連接，對元件靜態及動態性能之影響，以提出具體化的優化設計準則，滿足未來低壓高效率功率元件發展需求。 首先，本研究針對傳統接觸式場板 LDMOS (Conventional Contact Field Plate LDMOS, Conv. CFP LDMOS) 與高介電常數場板 LDMOS (High-k Field Plate LDMOS, HK FP LDMOS) 進行場板設計之最佳化並探討靜態優值 (Static Figure-of-Merit, FOMS = BV2/Ron,sp) 的表現。調整參數包含場板至汲極端之距離、場板氧化層厚度，以及針對 HK FP LDMOS 的緩衝層厚度、 HK 層厚度，與不同場板連接策略：閘極連接 (HK Gate-Connected FP LDMOS, HK GFP LDMOS)、浮接 (HK Floating FP LDMOS, HK FFP LDMOS)，與源極連接 (HK Source-Connected FP LDMOS, HK SFP LDMOS)。結果顯示，使用 HK 材料能使橫向電場分布更加均勻，相較 Conv. CFP LDMOS 由兩電場主峰主導， HK FP LDMOS 能有接近三峰值的表現，使其有更佳 FOMS 的表現。相較於 Conv. CFP LDMOS，HK GFP LDMOS 其崩潰電壓提升約16%、特徵導通電阻降低約11%，使 FOMS 提升約52%。而 HK FFP 與 SFP LDMOS 崩潰電壓亦提升約16%、特徵導通電阻降低約 2%， FOMS 則提升約38%。 本研究接著分析動態性能。HK GFP LDMOS因額外並聯的場板與汲極電容，導致閘極對汲極電荷 (Gate-to-Drain Charge, QGD) 增加約3.87倍，並使動態優值 (Dynamic Figure-of-Merit, FOMD = QGD,spRon,sp) 較Conv. CFP LDMOS劣化3.38 倍，對高速應用造成限制。相較之下，源極連接之 HK SFP LDMOS 則在FOMS及FOMD之間達到較為折衷之設計。在 BV = 32 V 與 37 V 限制條件下，HK GFP LDMOS 之 FOMD 分別為 Conv. CFP LDMOS 的 3.04 倍與 2.91 倍；HK FFP LDMOS 則為 2.40 倍與 2.32 倍；HK SFP LDMOS 僅小幅增加約 10% 與 6%，顯示 HK SFP LDMOS 能在兼顧優異 FOMS 的同時，仍有效控制切換損耗，展現出靜態與動態性能較平衡的特性。 研究成果不僅證實高介電常數場板氧化層對於橫向電場分布均勻性及漂移區空乏能力的顯著貢獻，亦提供不同場板連接策略下LDMOS靜態與動態性能的設計參考，為未來低壓高效能功率晶片提供重要的理論基礎與實務應用價值。

With the increasing demands for high efficiency and high reliability in power management and high-speed interface circuits, the Lateral Double-diffused MOSFET (LDMOS) has become an indispensable key device in modern Bipolar-CMOS-DMOS (BCD) processes. The field plate structures in conventional LDMOS mostly use silicon dioxide (SiO2) as the field plate oxide layer. Due to its relatively low dielectric constant of approximately 3.9, its ability to modulate the electric field distribution in the drift region is limited, making it difficult to achieve further performance improvements. Previous studies have proposed introducing high-k (HK) dielectric materials into the field plate oxide layer to improve the electric field distribution, thereby enhancing the breakdown voltage (BV) and reducing the specific on-state resistance (Ron,sp). However, the application of HK materials has mostly focused on high-voltage (BV > 100 V) devices and commonly uses perovskite materials, which face issues such as lattice mismatch and interface charges, limiting their compatibility and reliability with CMOS processes. Moreover, there is a lack of systematic investigation on field plate connection strategies in the literature. Therefore, this study focuses on low-voltage (BV ≈ 40 V) applications, adopting hafnium dioxide (HfO₂, k ≈ 22), which has high compatibility with CMOS processes, as the field plate oxide layer. A systematic analysis of different field plate connection strategies, including gate-connected, floating, and source-connected configurations, is conducted to evaluate their impact on both static and dynamic device performance, aiming to establish concrete optimization design guidelines to meet the demands of future low-voltage, high-efficiency power devices. First, this study performs design optimization of the field plate for both conventional contact field plate LDMOS (Conv. CFP LDMOS) and high-k field plate LDMOS (HK FP LDMOS), and evaluates their static figure of merit (FOMS = BV²/Ron,sp). The adjusted parameters include the distance from the field plate to the drain edge, field plate oxide thickness, and, for HK FP LDMOS, the buffer layer thickness, HK layer thickness, and different connection strategies: gate-connected (HK GFP LDMOS), floating (HK FFP LDMOS), and source-connected (HK SFP LDMOS). The results show that using HK materials enables a more uniform lateral electric field distribution; compared to Conv. CFP LDMOS, which exhibits two dominant field peaks, HK FP LDMOS achieves an approximately three-peak distribution, thus enhancing its FOMS performance. Compared to Conv. CFP LDMOS, HK GFP LDMOS exhibits an approximately 16% increase in BV, an approximately 11% reduction in Ron,sp, and about a 52% improvement in FOMS. HK FFP and SFP LDMOS also show an approximate 16% increase in BV, a roughly 2% reduction in Ron,sp, and a 38% improvement in FOMS. This study further analyzes the dynamic performance. Due to the additional parallel capacitance between the field plate and drain, HK GFP LDMOS exhibits an increase in gate-to-drain charge (QGD) by approximately 3.87 times, resulting in a dynamic figure of merit (FOMD = QGD,sp × Ron,sp) degradation by about 3.38 times compared to Conv. CFP LDMOS, limiting its suitability for high-speed applications. In contrast, the HK SFP LDMOS achieves a more balanced trade-off between FOMS and FOMD. Under BV constraint conditions of 32 V and 37 V, the FOMD of HK GFP LDMOS is 3.04 times and 2.91 times that of Conv. CFP LDMOS, respectively; HK FFP LDMOS is 2.40 times and 2.32 times, respectively; while HK SFP LDMOS increases only by about 10% and 6%, respectively, indicating that HK SFP LDMOS can maintain excellent FOMS while effectively controlling switching losses, thus exhibiting a more balanced static and dynamic performance. The results not only confirm the significant contribution of high-k field plate oxide layers in improving the lateral electric field uniformity and drift region depletion capability but also provide valuable design references for LDMOS static and dynamic performance under different field plate connection strategies. This study offers an important theoretical foundation and practical value for the development of future low-voltage, high-performance power chips.