透過接觸與介面工程提升二維P型電晶體性能

Abstract

二維過渡金屬二硫屬化合物的出現為下一代邏輯電晶體的微縮提供了一條極具潛力的發展路徑，超越了傳統矽基技術。利用過渡金屬二硫屬化合物的互補式金屬氧化物半導體架構可實現極端的垂直微縮，需要高效能的P型與 N型電晶體以達成有效整合。雖然二硫化鉬N型電晶體展現出高導通電流密度及低接觸電阻，但二維P型電晶體仍面臨驅動電流密度不足、高接觸電阻、以及臨界電壓不匹配等挑戰，限制了其在邏輯電路中的應用。 在P型過渡金屬二硫屬化合物材料中，二硒化鎢由於其天然的P型特性和較高的電洞遷移率，被視為極具潛力的候選材料。然而，金屬誘導能隙態和缺陷誘導能隙態所造成的費米能級釘扎現象，導致其費米能級被固定於不利於電洞注入的位置，進而降低接觸效率，造成高接觸電阻，限制其器件效能。 為了解決費米能級釘扎問題，我們提出一種銻-鉑調控接觸策略，實現單層二硒化鎢電晶體中多數載子極性的可調控制。透過調整金屬銻介面層厚度，可將金屬接觸的有效功函數從4.19 eV 調控至 4.42eV。此策略使得單一二硒化鎢通道上同時實現高效N型與 P型電晶體，其電流密度分別達到P型電晶體為 170 µA/µm，N型電晶體為165 µA/µm (|VD| = 1 V)，展示了接觸調控技術在低成本二維互補式金屬氧化物半導體整合中的潛力。 然而，進一步分析發現通道低載子濃度及離子束微影於接觸區的轟擊限制了電晶體的效能。為解決此瓶頸，我們提出一種光微影誘導摻雜及介面調控技術，應用於 單層二硒化鎢P型電晶體。該技術可將接觸電阻4.8 kΩ·µm，並透過氧化鉬封裝層進一步降低至0.8 kΩ·μm，使得導通電流密度提升至420 μA/μm。此提升亦促使場效遷移率提高至75 cm²/V·s，並將電洞載子濃度提升1.4 倍。此外，該技術可實現有效功函數在 4.25 eV 至 4.55 eV 的可調性，進一步驗證了介面工程在提升二維電晶體效能方面的可行性。 最後，我們展示了基於二硒化鎢P型電晶體與二硫化鉬N型電晶體邏輯電路整合。透過優化接觸電阻與降低有效氧化層厚度，成功製作異質通道二維反相器，實現超過 10 V/V 的電壓增益、超過 80% 的噪聲容限、以及超低靜態功耗 (~7 pW 在 VDD = 1 V)。此研究標誌著低功耗、高效能二維互補式金屬氧化物半導體邏輯整合的重要進展。 本論文提供了一個系統性的接觸工程、摻雜技術與元件整合策略，克服二維電晶體的關鍵挑戰，推動可擴展、節能且高效能的二維反相器製程技術，加速新興奈米材料與次世代半導體技術的銜接。

The emergence of two-dimensional (2D) transition metal dichalcogenides (TMDs) presents a promising avenue for scaling next-generation logic transistors beyond silicon. TMDs based complementary metal-oxide-semiconductor (CMOS) technology offers strong potential for vertical scaling. To enable efficient integration, both high-performance n-type and p-type transistors are required. Molybdenum disulfide (MoS2) n-type transistors have shown excellent current delivery and low contact resistance (RC). However, the development of two-dimensional p-type transistors is still constrained by low current output, which hinder their application in logic circuits. Tungsten diselenide (WSe2) is a leading candidate among TMDs for hole transport channels, owing to its intrinsic p-type characteristics and favorable hole mobility. Despite these advantages, contact performance is limited by Fermi-level pinning (FLP), which arises from states introduced by metal interactions and structural imperfections at the interface. These interface states prevent proper alignment between the Fermi level and the valence band, thereby impeding efficient hole injection and contributing to elevated contact resistance. To mitigate the effects of FLP, we introduce an antimony-platinum (Sb-Pt) modulated contact strategy to enable tunable majority carrier polarity in monolayer WSe2 transistors. By adjusting the Sb interfacial layer thickness, the effective work function of the metal contact can be tuned from 4.42 eV to 4.19 eV. This approach achieves current densities of 170 µA/µm for p-FETs and 165 µA/µm for n-FETs at |VD| = 1 V, demonstrating the potential of contact modulation for CMOS integration. However, further analysis reveals that low carrier concentration and ion-beam bombardment at the contact region during lithography limit device performance. To address these challenges, a doping and interface engineering technique based on photolithography treatment is introduced for enhancing the performance of monolayer WSe2 p-type transistors. Using this method, the RC is reduced to 4.8 kΩ·µm and further improved to 0.8 kΩ·μm with MoOₓ encapsulation. As a result, the device exhibits a high on-state current of 420 μA/μm. These optimizations also enhance the field-effect mobility to 60 cm²/V·s and increase the hole carrier density by approximately 40 percent. Additionally, the effective work function is tunable from 4.25 to 4.55 eV, confirming the effectiveness of interface engineering in improving 2D transistor performance. Finally, a co-integrated logic circuit is demonstrated using WSe2 p-MOS and MoS2 n-MOS. Through optimized contact resistance and reduced effective oxide thickness, a hetero-channel 2D inverter is fabricated, achieving a voltage gain of >10 V/V, noise margin exceeding 80%, and ultra-low static power consumption (~ 7 pW at VDD = 1 V). This dissertation provides a systematic approach to contact engineering, doping, and device co-integration to overcome key challenges in 2D transistors. The findings pave the way for high-performance 2D CMOS electronics, bridging the gap between emerging nanomaterials and next-generation semiconductor technologies.