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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳志毅 | zh_TW |
| dc.contributor.advisor | Chih-I Wu | en |
| dc.contributor.author | 林禹彤 | zh_TW |
| dc.contributor.author | Yu-Tung Lin | en |
| dc.date.accessioned | 2025-07-11T16:12:22Z | - |
| dc.date.available | 2025-07-12 | - |
| dc.date.copyright | 2025-07-11 | - |
| dc.date.issued | 2025 | - |
| dc.date.submitted | 2025-07-01 | - |
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[105] Chou, A.-S.; Lin, Y.-T.; Lin, Y. C.; Hsu, C.-H.; Li, M.-Y.; Liew, S.-L.; Chou, S.-A.; Chen, H.-Y.; Chiu, H.-Y.; Ho, P.-H.; Hsu, M.-C.; Hsu, Y.-W.; Yang, N.; Woon, W.-Y.; Liao, S.; Hou, D.-H.; Chien, C.-H.; Chang, W.-H.; Radu, I.; Wu, C.-I.; Philip Wong, H.-S.; Wang, H. High-Performance Monolayer WSe2 p/n FETs via Antimony-Platinum Modulated Contact Technology towards 2D CMOS Electronics. In 2022 International Electron Devices Meeting (IEDM); IEEE, 2022; pp 7.2.1-7.2.4. [106] Li, M.; Zhang, X.; Zhang, Z.; Peng, G.; Zhu, Z.; Li, J.; Qin, S.; Zhu, M. Unipolar P-Type Monolayer WSe2 Field-Effect Transistors with High Current Density and Low Contact Resistance Enabled by van Der Waals Contacts. Nano Research 2024, 17 (11), 10162–10169. [107] Fang, H.; Chuang, S.; Chang, T. C.; Takei, K.; Takahashi, T.; Javey, A. High Performance Single Layered WSe2 p-FETs with Chemically Doped Contacts. Nano Lett. 2012, 12 (7), 3788–3792. [108] Chen, S.; Zhang, Y.; King, W. P.; Bashir, R.; van der Zande, A. M. Extension Doping with Low‐Resistance Contacts for P‐Type Monolayer WSe2 Field‐Effect Transistors. Adv. Electron. Mater. 2024. [109] Ho, P.-H.; Yang, Y.-Y.; Chou, S.-A.; Cheng, R.-H.; Pao, P.-H.; Cheng, C.-C.; Radu, I.; Chien, C.-H. High-Performance WSe2 Top-Gate Devices with Strong Spacer Doping. Nano Lett. 2023, 23 (22), 10236–10242. [110] Yu, L.; Zubair, A.; Santos, E. J. G.; Zhang, X.; Lin, Y.; Zhang, Y.; Palacios, T. High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits. Nano Lett. 2015, 15 (8), 4928–4934. [111] Yeh, C.-H.; Liang, Z.-Y.; Lin, Y.-C.; Chen, H.-C.; Fan, T.; Ma, C.-H.; Chu, Y.-H.; Suenaga, K.; Chiu, P.-W. Graphene–Transition Metal Dichalcogenide Heterojunctions for Scalable and Low-Power Complementary Integrated Circuits. ACS Nano 2020, 14 (1), 985–992. [112] Guan, S.-X.; Yang, T. H.; Yang, C.-H.; Hong, C.-J.; Liang, B.-W.; Simbulan, K. B.; Chen, J.-H.; Su, C.-J.; Li, K.-S.; Zhong, Y.-L.; Li, L.-J.; Lan, Y.-W. Monolithic 3D Integration of Back-End Compatible 2D Material FET on Si FinFET. NPJ 2D Mater. Appl. 2023, 7 (1), 9. [113] Piacentini, A.; Polyushkin, D. K.; Uzlu, B.; Grundmann, A.; Heuken, M.; Kalisch, H.; Vescan, A.; Wang, Z.; Lemme, M. C.; Mueller, T.; Neumaier, D. Flexible Complementary Metal‐Oxide‐Semiconductor Inverter Based on 2D P‐type WSe2 and N‐type MoS2. physical status solidi (a) 2024, 221 (10). [114] Huang, X.; Liu, C.; Zhou, P. 2D Semiconductors for Specific Electronic Applications: From Device to System. NPJ 2D Mater. Appl. 2022, 6 (1), 51. [115] Kim, K. S.; Seo, S.; Kwon, J.; Lee, D.; Kim, C.; Ryu, J.-E.; Kim, J.; Song, M.-K.; Suh, J. M.; Jung, H.-G.; Jo, Y.; Ahn, H.; Lee, S.; Cho, K.; Jeon, J.; Seol, M.; Park, J.-H.; Kim, S. W.; Kim, J. Seamless Monolithic Three-Dimensional Integration of Single-Crystalline Films by Growth. 2023. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/97691 | - |
| dc.description.abstract | 二維過渡金屬二硫屬化合物的出現為下一代邏輯電晶體的微縮提供了一條極具潛力的發展路徑，超越了傳統矽基技術。利用過渡金屬二硫屬化合物的互補式金屬氧化物半導體架構可實現極端的垂直微縮，需要高效能的P型與 N型電晶體以達成有效整合。雖然二硫化鉬N型電晶體展現出高導通電流密度及低接觸電阻，但二維P型電晶體仍面臨驅動電流密度不足、高接觸電阻、以及臨界電壓不匹配等挑戰，限制了其在邏輯電路中的應用。
在P型過渡金屬二硫屬化合物材料中，二硒化鎢由於其天然的P型特性和較高的電洞遷移率，被視為極具潛力的候選材料。然而，金屬誘導能隙態和缺陷誘導能隙態所造成的費米能級釘扎現象，導致其費米能級被固定於不利於電洞注入的位置，進而降低接觸效率，造成高接觸電阻，限制其器件效能。 為了解決費米能級釘扎問題，我們提出一種銻-鉑調控接觸策略，實現單層二硒化鎢電晶體中多數載子極性的可調控制。透過調整金屬銻介面層厚度，可將金屬接觸的有效功函數從4.19 eV 調控至 4.42eV。此策略使得單一二硒化鎢通道上同時實現高效N型與 P型電晶體，其電流密度分別達到P型電晶體為 170 µA/µm，N型電晶體為165 µA/µm (|VD| = 1 V)，展示了接觸調控技術在低成本二維互補式金屬氧化物半導體整合中的潛力。 然而，進一步分析發現通道低載子濃度及離子束微影於接觸區的轟擊限制了電晶體的效能。為解決此瓶頸，我們提出一種光微影誘導摻雜及介面調控技術，應用於 單層二硒化鎢P型電晶體。該技術可將接觸電阻4.8 kΩ·µm，並透過氧化鉬封裝層進一步降低至0.8 kΩ·μm，使得導通電流密度提升至420 μA/μm。此提升亦促使場效遷移率提高至75 cm²/V·s，並將電洞載子濃度提升1.4 倍。此外，該技術可實現有效功函數在 4.25 eV 至 4.55 eV 的可調性，進一步驗證了介面工程在提升二維電晶體效能方面的可行性。 最後，我們展示了基於二硒化鎢P型電晶體與二硫化鉬N型電晶體邏輯電路整合。透過優化接觸電阻與降低有效氧化層厚度，成功製作異質通道二維反相器，實現超過 10 V/V 的電壓增益、超過 80% 的噪聲容限、以及超低靜態功耗 (~7 pW 在 VDD = 1 V)。此研究標誌著低功耗、高效能二維互補式金屬氧化物半導體邏輯整合的重要進展。 本論文提供了一個系統性的接觸工程、摻雜技術與元件整合策略，克服二維電晶體的關鍵挑戰，推動可擴展、節能且高效能的二維反相器製程技術，加速新興奈米材料與次世代半導體技術的銜接。 | zh_TW |
| dc.description.abstract | The emergence of two-dimensional (2D) transition metal dichalcogenides (TMDs) presents a promising avenue for scaling next-generation logic transistors beyond silicon. TMDs based complementary metal-oxide-semiconductor (CMOS) technology offers strong potential for vertical scaling. To enable efficient integration, both high-performance n-type and p-type transistors are required. Molybdenum disulfide (MoS2) n-type transistors have shown excellent current delivery and low contact resistance (RC). However, the development of two-dimensional p-type transistors is still constrained by low current output, which hinder their application in logic circuits.
Tungsten diselenide (WSe2) is a leading candidate among TMDs for hole transport channels, owing to its intrinsic p-type characteristics and favorable hole mobility. Despite these advantages, contact performance is limited by Fermi-level pinning (FLP), which arises from states introduced by metal interactions and structural imperfections at the interface. These interface states prevent proper alignment between the Fermi level and the valence band, thereby impeding efficient hole injection and contributing to elevated contact resistance. To mitigate the effects of FLP, we introduce an antimony-platinum (Sb-Pt) modulated contact strategy to enable tunable majority carrier polarity in monolayer WSe2 transistors. By adjusting the Sb interfacial layer thickness, the effective work function of the metal contact can be tuned from 4.42 eV to 4.19 eV. This approach achieves current densities of 170 µA/µm for p-FETs and 165 µA/µm for n-FETs at |VD| = 1 V, demonstrating the potential of contact modulation for CMOS integration. However, further analysis reveals that low carrier concentration and ion-beam bombardment at the contact region during lithography limit device performance. To address these challenges, a doping and interface engineering technique based on photolithography treatment is introduced for enhancing the performance of monolayer WSe2 p-type transistors. Using this method, the RC is reduced to 4.8 kΩ·µm and further improved to 0.8 kΩ·μm with MoOₓ encapsulation. As a result, the device exhibits a high on-state current of 420 μA/μm. These optimizations also enhance the field-effect mobility to 60 cm²/V·s and increase the hole carrier density by approximately 40 percent. Additionally, the effective work function is tunable from 4.25 to 4.55 eV, confirming the effectiveness of interface engineering in improving 2D transistor performance. Finally, a co-integrated logic circuit is demonstrated using WSe2 p-MOS and MoS2 n-MOS. Through optimized contact resistance and reduced effective oxide thickness, a hetero-channel 2D inverter is fabricated, achieving a voltage gain of >10 V/V, noise margin exceeding 80%, and ultra-low static power consumption (~ 7 pW at VDD = 1 V). This dissertation provides a systematic approach to contact engineering, doping, and device co-integration to overcome key challenges in 2D transistors. The findings pave the way for high-performance 2D CMOS electronics, bridging the gap between emerging nanomaterials and next-generation semiconductor technologies. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-07-11T16:12:22Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2025-07-11T16:12:22Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 致謝 i
摘要 iii Abstract v Contents vii List of Figures x List of Tables xviii Chapter 1. Introduction 1 1.1. Overview of two-dimensional materials 4 1.2. Transition Metal Dichalcogenides in logic devices 6 1.2.1. Origins and impacts of Fermi-Level Pinning (FLP) 8 1.2.2. Strategies to relieve FLP in n-type transistors 11 1.3. Challenges in TMDs p-type transistors 14 1.4. Scope and organization of this dissertation 19 Chapter 2. Experiments & Methodologies 21 2.1. Growth mechanism of monolayer MoS2 and WSe2 21 2.2. Characterization of material quality 25 2.2.1. Optical microscopy (OM) 25 2.2.2. Raman and Photoluminescence (PL) spectroscopy 25 2.2.3. Atomic force microscopy (AFM) 28 2.2.4. Scanning electron microscopy (SEM) 30 2.2.5. Transmission electron microscopy (TEM) 32 2.2.6. X-ray diffraction (XRD) 34 2.3. Interface and electronic structure characterization 36 2.3.1. X-ray photoelectron spectroscopy (XPS) 36 2.3.2. Ultraviolet photoelectron spectroscopy (UPS) 39 2.3.3. Depth profiling analysis 40 2.4. Device fabrication and electrical measurement system 42 2.4.1. Transfer process 42 2.4.2. Rapid thermal annealing (RTA) 43 2.4.3. Lithography system 44 2.4.4. Physical vapor deposition (PVD) system 46 2.4.5. Patterning and lift-off process 48 2.4.6. Electrical measurement system 50 2.5. Quantitative analysis of transistor performance metrics 53 2.5.1. Threshold voltage (VTH) 53 2.5.2. Subthreshold swing (SS) 54 2.5.3. On-off ratio 55 2.5.4. Mobility 56 2.5.5. Contact resistance 58 2.6. Static performance evaluation of CMOS inverters 61 2.6.1. Voltage transfer characteristics (VTC) 61 2.6.2. Switching threshold voltage (VM) 63 2.6.3. Gain 63 2.6.4. Noise margins 64 2.6.5. Static power consumption 65 Chapter 3. Antimony-Platinum contacts for n/p-type monolayer WSe2 transistors 67 3.1. Device fabrication and morphological characterization 68 3.2. Electrical characterization and polarity outcomes 70 3.3. Statistical analysis of device performance 72 3.4. Interface analysis and material characterization 75 3.5. Encapsulation strategy for performance enhancement 85 3.6. Summary 91 Chapter 4. Photolithography-assisted surface treatment for WSe2 p-type transistors 93 4.1. Fabrication Process 94 4.2. Statistic electrical property in long-channel devices 96 4.3. Doping mechanisms through 1L-WSe2 channel 100 4.4. Statistic electrical property in short-channel devices 105 4.5. Mechanisms of contact modulation 110 4.6. Ultralow RC and performance boost via MoOx doping 119 4.7. Summary 123 Chapter 5. CMOS integration based on TMDs heterogenous channel 125 5.1. CMOS inverter fabrication and device integration 125 5.2. Electrical characteristics of individual n/p-FETs 128 5.3. Inverter performance metrics and benchmark 129 5.4. Summary 134 Chapter 6. Conclusion and future work 135 Chapter 7. Reference 137 Chapter 8. Publication list 149 | - |
| dc.language.iso | en | - |
| dc.subject | 費米能階釘扎 | zh_TW |
| dc.subject | 互補式電路整合 | zh_TW |
| dc.subject | 單層二硒化鎢 | zh_TW |
| dc.subject | 光微影摻雜 | zh_TW |
| dc.subject | 接觸工程 | zh_TW |
| dc.subject | 二維材料 | zh_TW |
| dc.subject | Contact Engineering | en |
| dc.subject | Fermi-Level Pinning | en |
| dc.subject | 2D materials | en |
| dc.subject | CMOS Integration | en |
| dc.subject | Monolayer WSe2 | en |
| dc.subject | Photolithography-Induced Doping | en |
| dc.title | 透過接觸與介面工程提升二維P型電晶體性能 | zh_TW |
| dc.title | Enhancing Two-dimensional P-Type Transistors Performance via Contact and Interface Engineering | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-2 | - |
| dc.description.degree | 博士 | - |
| dc.contributor.oralexamcommittee | 周昂昇;李明洋;李宗恩;陳美杏;張子璿;吳肇欣 | zh_TW |
| dc.contributor.oralexamcommittee | Ang-Sheng Chou;Ming-Yang Li;Tsung-En Lee;Mei-Hsin Chen;Tzu-Hsuan Chang;Chao-Hsin Wu | en |
| dc.subject.keyword | 二維材料,費米能階釘扎,接觸工程,光微影摻雜,單層二硒化鎢,互補式電路整合, | zh_TW |
| dc.subject.keyword | 2D materials,Fermi-Level Pinning,Contact Engineering,Photolithography-Induced Doping,Monolayer WSe2,CMOS Integration, | en |
| dc.relation.page | 151 | - |
| dc.identifier.doi | 10.6342/NTU202501401 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2025-07-02 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 光電工程學研究所 | - |
| dc.date.embargo-lift | 2030-06-29 | - |
| 顯示於系所單位： | 光電工程學研究所 | |
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