0.5奈米技術下之互補式場效電晶體NFET堆疊PFET 與 PFET堆疊NFET配置的16KB SRAM巨集分析

Abstract

隨著技術節點的不斷推進和製程技術的進步，積體電路中的電晶體數量持續增加，從而提升操作速度和整體效能。隨著這些變化，電晶體的閘極長度也在逐步縮小。互補式場效電晶體（Complementary Field-Effect Transistor, CFET）被廣泛認為是一種具有重大潛力的前瞻技術，該技術通過將NFET和PFET垂直堆疊的方式來實現。然而，對於NFET和PFET的最佳配置仍然沒有一個公認的標準答案。鑒於此，本論文旨在從電路設計的角度出發，探討CFET結構中的最佳配置方式。 本文共分為三個主要部分。第一部分詳細介紹了互補式場效電晶體的元件結構，並詳細說明了CFET垂直結構N/P（NFET在上，PFET在下）和P/N（PFET在上，NFET在下）兩種配置的技術參數和性質。第二部分則聚焦於這兩種配置在邏輯電路設計中的實際應用，研究的電路包括反向器 ( Inverter )、二輸入反或閘 (Two-input NOR, NOR2)、三輸入反或閘（Three-input NOR, NOR3），並分析了佈局設計與三維結構如何影響電路特性。第三部分則探討了N/P和P/N配置在16KB SRAM記憶體及其周邊電路設計中的應用，包括SRAM 記憶體單元 ( SRAM Bitcell )、感測放大器、預充電路、讀寫電路、列解碼器和行解碼器與多工器。本論文不僅分析了N/P及P/N每種配置的設計優勢和對電路穩定性的影響，還在實際應用中提供了數據和性能比較。研究結果顯示，在各種應用場景中，N/P和P/N配置各自具有獨特的優勢，N/P 配置在讀寫時間（Read/Write Time）上相對於 P/N 配置具有12.29%和15.37%的優勢，在讀寫能量（Read/Write Energy）上也分別領先2.03%和8.34%。然而，P/N 配置在面積方面表現出色，比 N/P 配置縮小了28.9%，並且在讀寫功耗（Read/Write Power）上也有1.39%和1.45%的優勢，因此可以根據具體應用選擇最佳架構。這項研究將為埃米世代及先進技術節點微縮方面提供重要的見解。

As technology nodes continue to scale and process technologies advance, the number of transistors integrated into a single chip increases significantly to enhance system performance and efficiency. To support this trend, transistor gate lengths are continuously reduced. Among emerging device architectures, Complementary Field-Effect Transistors (CFETs), which vertically stack NFET and PFET devices, have emerged as a highly promising solution, offering a new direction in semiconductor design. This novel structure aims to overcome the performance limitations encountered by traditional FET technologies at deeply scaled nodes. However, the optimal stacking configuration of NFET and PFET within CFETs remains undetermined. This thesis investigates the impact of CFET configurations from a circuit-level perspective, with the goal of identifying optimal design strategies for improved circuit performance. This work is divided into three parts. The first part introduces the CFET device structure and provides a detailed comparison of the electrical characteristics of two stacking configurations: N/P (NFET over PFET) and P/N (PFET over NFET). The second part explores the implications of these configurations in logic circuit design, analyzing key elements such as inverters, two-input NOR gates, and three-input NOR gates. It further examines how layout constraints and three-dimensional integration affect performance and area efficiency. The third part applies both N/P and P/N configurations to the design of a 16KB SRAM and its peripheral circuitry, including bitcells, sense amplifiers, precharge circuits, read/write paths, and row/column decoders. This section evaluates the design trade-offs associated with each configuration, including performance, energy efficiency, stability, and area. Experimental results reveal that compared to the P/N configuration, the N/P configuration offers superior speed and energy performance, achieving improvements of 12.29% and 15.37% in read/write latency and 2.03% and 8.34% in read/write energy, respectively. In contrast, the P/N configuration demonstrates better area efficiency, reducing layout area by 28.9%, and exhibits slight advantages in read/write power consumption (1.39% and 1.45%, respectively). These findings suggest that each configuration offers distinct benefits depending on the target application, and the selection should be guided by system-level priorities such as speed, power, and area. This study provides valuable insights into CFET-based design and offers circuit-level guidelines for future technology scaling in advanced nodes.